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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 85  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
IPSJ-SLDM, VLD 2011-05-19
09:30
Fukuoka Kitakyushu International Conference Center Super-resolution by UsingWeighted Adders with Selector Logics
Hiromine Yoshihara, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.) VLD2011-6
 [more] VLD2011-6
pp.27-32
VLD 2011-03-02
14:00
Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center Exact, Fast and Flexible Two-level Cache Simulation for Embedded Systems
Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.) VLD2010-118
In hierarchical cache configurations, L1 cache uses LRU as cache
replacement policy but L2 and/or L3 caches use FIFO du... [more]
VLD2010-118
pp.13-18
VLD 2011-03-02
15:05
Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center An Energy-efficient ASIP Synthesis Method Using Scratchpad Memory and Code Placement Optimization
Yoshinori Shimada, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2010-120
In this paper, we propose an energy-efficient ASIP synthesis method using scratchpad memory.
Due to the fact that a si... [more]
VLD2010-120
pp.25-30
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-11-30
09:30
Fukuoka Kyushu University Speeding-up Exact and Fast L1 Cache Configuration Simulation based on FIFO Replacement Policy
Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.) VLD2010-64 DC2010-31
The number of sets, block size and associativity determine processor's cache configuration. Particularly in embedded sys... [more] VLD2010-64 DC2010-31
pp.55-60
VLD, IPSJ-SLDM 2010-05-19
15:30
Fukuoka Kitakyushu International Conference Center High-Level Synthesis with Floorplan for GDR Architectures and its Evaluation
Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2010-1
 [more] VLD2010-1
pp.19-24
VLD 2010-03-10
16:55
Okinawa   [Invited Talk] Changing Organization through Continuous Data Collection with Business Microscope
Koji Ara, Nobuo Sato, Kazuo Yano (Hitachi), Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda) VLD2009-106
 [more] VLD2009-106
pp.43-47
ITE-AIT, IE, ITE-HI, ITE-ME, ITS 2010-02-16
13:25
Hokkaido Graduate School of Information and Technology, Hokkaido Univ. A Pedestrian Positioning System Using Road Traffic Signs and Landmarks Based on Current Location Recognition
Tomoyuki Kojima, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.) ITS2009-64 IE2009-158
Mobile-GPS is generally used for pedestrian positioning on mobile devices such as mobile phones and PDAs.However mobile-... [more] ITS2009-64 IE2009-158
pp.153-158
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-26
17:10
Kanagawa Keio Univ (Hiyoshi Campus) A Dedicated Functional Unit Synthesis Algorithm with MISO Structures based on Partial Matching
Norihiro Hashimoto, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2009-83 CPSY2009-65 RECONF2009-68
Requirement for application-specific processor is really increasing recently, however, it takes much time to design a pr... [more] VLD2009-83 CPSY2009-65 RECONF2009-68
pp.89-94
USN, AN, MoNA
(Joint)
2010-01-22
13:00
Shizuoka Actcity Hamamatsu Connectivity-based and Load-balanced Cluster Routing for Mobile Ad hoc Networks
Yusuke Itabashi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) AN2009-62
Conventional routing protocols in ad hoc networks have problems that links are broken and control signals expand when in... [more] AN2009-62
pp.85-90
USN, AN, MoNA
(Joint)
2010-01-22
13:50
Shizuoka Actcity Hamamatsu Multicast routing protocol with collision avoidance in multi-group wireless ad-hoc networks
Hiroyuki Takeuchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) AN2009-64
In a wireless ad hoc network, multicasting is expected to deliver data to more nodes in a limited bandwidth. Multicastin... [more] AN2009-64
pp.95-100
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-02
15:40
Kochi Kochi City Culture-Plaza Two-level Cache Simulation with L2 Unified Cache for Embedded Applications
Yuta Kobayashi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2009-47 DC2009-34
In this paper, we propose a two-level cache simulation method with L2 unified cache for embedded applications. It simula... [more] VLD2009-47 DC2009-34
pp.37-42
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-02
16:00
Kochi Kochi City Culture-Plaza Simulation-Based Bus Width Optimization for Two-Level Cache
Shinta Watanabe, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2009-48 DC2009-35
In this paper, we propose a simulation-based bus width and cache configuration optimization approach for two-level cache... [more] VLD2009-48 DC2009-35
pp.43-48
VLD 2009-09-25
11:05
Osaka Osaka University High Throughput Irregular LDPC Decoder Based on High-Efficiency Column Operation Unit for IEEE 802.11n Standard
Akiyuki Nagashima, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2009-38
Low Density Parity Check (LDPC) code is expected to be an error orrecting code for next generation networks since it sho... [more] VLD2009-38
pp.51-56
VLD 2009-09-25
11:30
Osaka Osaka University DFG Mapping for Flexible Engine/Generic ALU Array and Its Dedicated Synthesis Algorithm
Ryo Tamura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Makoto Satoh (Hitachi Ltd.) VLD2009-39
Reconfigurable processors are those whose contexts are dynamically reconfigured while they are working. We focus on a r... [more] VLD2009-39
pp.57-62
VLD, IPSJ-SLDM 2009-05-20
14:55
Fukuoka Kitakyushu International Conference Center A Weighted-Sum Circuit Using Selector Logic By Transforming Bit-Level Operations
Tomoaki Hara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Motonobu Tonomura (Dai Nippon Printing Corp.) VLD2009-2
Consider a weighted-sum operation, sum of whose weights becomes one.
This operation can be applied to various image pro... [more]
VLD2009-2
pp.7-12
VLD 2009-03-12
15:40
Okinawa   A Task Mapping Algorithm for Task Chaining Network Processor by Backtracking
Keita Saito, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-151
To meet increasing demands of link speeds and complex network applications, network processor is required because it has... [more] VLD2008-151
pp.147-152
VLD 2009-03-12
16:05
Okinawa   Delay Reduction Algorithm by Balancing Distribution of Traffic for Odd-Even Turn Model in NoCs
Shingo Wakita, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-152
It is necessary to suppress the average delay to low when the packet is forwarded from a source node to the destination ... [more] VLD2008-152
pp.153-158
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-29
17:00
Kanagawa   Fast Module Placement in Floorplan-aware High-level Synthesis
Wataru Sato, Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-107 CPSY2008-69 RECONF2008-71
As device feature size decreases, interconnect delay becomes the dominating factor of total delay. Therefore it is neces... [more] VLD2008-107 CPSY2008-69 RECONF2008-71
pp.93-98
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-29
17:25
Kanagawa   A Fast SIMD Processing Unit Synthesis Method with Optimal Pipeline Architecture for Application-specific Processors
Takayuki Watanabe, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-108 CPSY2008-70 RECONF2008-72
Small area, high performance and high productivity are required for application-specific processors in embedded systems.... [more] VLD2008-108 CPSY2008-70 RECONF2008-72
pp.99-104
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-30
12:20
Kanagawa   A Multi-layer Bus Architecture Optimization Algorithm for MPSoC in Embedded Systems
Harunobu Yoshida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Masayoshi Tachibana (KUT) VLD2008-115 CPSY2008-77 RECONF2008-79
In this paper, we propose an on-chip bus optimization algorithm for a multi-layer bus architecture. Our algorithm effici... [more] VLD2008-115 CPSY2008-77 RECONF2008-79
pp.141-146
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