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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| AP | 2023-02-17 16:50 |
Miyagi | Tohoku University, Aobayama Campus (Primary: On-site, Secondary: Online) |
A Leaky Wave Antenna with Dielectric Slab on Perforated Dielectric Spacer Takuya Kaji, Hiroyasu Sato, Qiang Chen (Tohoku Univ.), Shimpei Nagae, Akira Kumagai, Osamu Kagaya (AGC)  AP2022-233 |
In this report, we propose and investigate a leaky wave antenna with dielectric slab on perforated dielectric spacer. Th... [more] | AP2022-233 pp.200-203 |
| AP | 2021-10-07 14:25 |
Online | Online | [Poster Presentation]
Design of Leaky Wave Glass Antenna at C-Band Takuya Kaji, Hiroyasu Sato, Chen Qiang (Tohoku Univ.), Simpei Nagae, Akira Kumagai, Yasuo Morimoto, Osamu Kagaya (AGC) AP2021-91 |
A leaky wave antenna has been reported in which a dielectric plate with a high dielectric constant is placed in front of... [more] | AP2021-91 pp.89-93 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2017-03-09 15:30 |
Okinawa | Kumejima Island | Approach to Direct Memory Access for Tamper Resistant System using Secure Processor Rihito Suzuki, Takuya Kajiwara, Mizuki Miyanaga, Hidetsugu Irie, Shuichi Sakai (UTokyo) CPSY2016-138 DC2016-84 |
In an environment using secure processor to support secure program execution, because of its integrity check mechanism, ... [more] | CPSY2016-138 DC2016-84 pp.39-44 |
| CPSY, IPSJ-ARC | 2016-10-06 10:00 |
Chiba | Makuhari-messe | [Poster Presentation]
Multi-Processor System Design with Secure Processors Takuya Kajiwara, Mizuki Miyanaga, Hidetsugu Irie, Shuichi Sakai (UTokyo) CPSY2016-43 |
A secure processor enables secure computing by protecting data from malicious users by encryption of data and integri... [more] |
CPSY2016-43 pp.7-10 |
| RECONF | 2014-09-18 14:10 |
Hiroshima | Prototype of fault tolerant FPGA using 65nm CMOS process Motoki Amagasaki, Takuya Kajiwara, Kentaro Fujisawa, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-18 |
我々はSoC（System on a Chip）に搭載されるFPGA-IP（Field Programmable Gate Array Intellectual Property）コアに焦点をあてたFT-FPGA（Fault Tolera... [more] |
RECONF2014-18 pp.7-12 |
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| RECONF | 2014-06-12 11:15 |
Miyagi | Katahira Sakura Hall | Three-dimensional FPGA Structure using High-speed Serial Communication Takuya Kajiwara, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-7 |
The three-dimensional (3D) integrated circuit technology is expected to continually improve the LSI (Large Scale Integra... [more] | RECONF2014-7 pp.31-36 |
| EE | 2014-01-23 16:35 |
Miyazaki | MIYAZAKI KANKO HOTEL | An Experimental Study on Power Packet Dispatching Network for Multipath Routing Naoaki Fujii, Ryo Takahashi, Takuya Kajiyama, Takashi Hikihara (Kyoto Univ.) EE2013-38 |
Recently, a power packet dispatching system was proposed as one of the new power distribution systems, which realizes to... [more] | EE2013-38 pp.43-48 |
| EE, IEE-SPC | 2012-07-31 09:00 |
Nara | An Experimental Study on Pulse Shape and Cable Characteristics for Power Packet Transmission Takuya Kajiyama, Takafumi Okuda, Ryo Takahashi, Takashi Hikihara (Kyoto Univ.) EE2012-9 |
Power packet transmission system is a new power distribution system. This system is based on a concept of packet communi... [more] | EE2012-9 pp.45-49 |
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