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Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF 2009-05-14
13:00		 Fukui   Performance Evaluation of Reconfigurable Processor Hy-DiSC based on MeP Hardware Extension
Ken'ichi Umeda, Takuro Uchida, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ) RECONF2009-1		 We have developed the reconfigurable processor Hy-DiSC for stream processing. Hy-DiSC processor consists of MeP and DS-H... [more] RECONF2009-1
pp.1-6
RECONF 2008-05-22
14:50		 Fukushima The University of Aizu Development of Compiler for Dynamic Reconfigurable Architecture DS-HIE which Adopts Digit-serial Computation
Yasuhiro Nishinaga, Takuro Uchida, Tetsuya Zuyama, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2008-5		 In our laboratory, to realize speedup of the streaming processing for small scale systems such as embeded systems, we ha... [more] RECONF2008-5
pp.25-30
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2007-11-22
09:25		 Fukuoka Kitakyushu International Conference Center Performance evaluation of reconfigurable architecture based on digit-serial computation
Takuro Uchida, Tetsuya Zuyama, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2007-44		 We have developed core architecture which has RISC processor and DS-HIE reconfigurable architecture.
This architecture ... [more]		 RECONF2007-44
pp.7-12
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