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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 10 of 10  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-03
10:40
Kochi Kochi City Culture-Plaza An Approach to Dependable Chip Multiprocessors with Process Pair and Swap Mechanism
Tomohide Nagai, Masashi Imai, Takashi Nanya (Univ. of Tokyo) VLD2009-51 DC2009-38
With the down scale of technology and the increase of transistor count, future processors are expected to be more suscep... [more] VLD2009-51 DC2009-38
pp.67-72
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2008-11-19
11:15
Fukuoka Kitakyushu Science and Research Park Leakage Power Reduction Method for Dual-Rail Four-Phase Asynchronous Circuits Using Multi-Vth Transistors
Koei Takada, Masashi Imai, Hiroshi Nakamura, Takashi Nanya (U. of Tokyo) VLD2008-90 DC2008-58
Dual-rail four-phase asynchronous circuits are well-known for their benefits in terms of delay variation tolerance. On t... [more] VLD2008-90 DC2008-58
pp.183-188
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2007-11-20
10:55
Fukuoka Kitakyushu International Conference Center A process-variation-aware low-power technique using current control
Kyun-dong Kim, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. of Tokyo) VLD2007-76 DC2007-31
Due to process variations, the difference of the operation speed between pipeline stages is increased,resulting in a num... [more] VLD2007-76 DC2007-31
pp.37-42
RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2006-11-28
16:10
Fukuoka Kitakyushu International Conference Center Proposal of a Behavioral Synthesis Method for Asynchronous Circuits in Bundled-data Implementation
Naohiro Hamada, Takao Konishi, Hiroshi Saito (The Univ. of Aizu), Tomohiro Yoneda (NII), Takashi Nanya (The Univ. of Tokyo)
 [more] VLD2006-63 DC2006-50
pp.71-76
DE, DC 2006-10-17
11:30
Tokyo   Tolerating Interaction Faults Originated From External Systems
Bogdan Tomoyuki Nassu, Takashi Nanya (Univ. of Tokyo)
This work introduces a new scenario and a fault model for tolerating interaction faults. This issue becomes more critica... [more] DE2006-120 DC2006-27
pp.7-12
ICD, SDM 2006-08-17
10:20
Hokkaido Hokkaido University Low power delay-insensitive asynchronous curcuits using 1-out-of-4 encoding.
Tomohiro Fujii, Masashi Imai, Hiroshi Nakamura, Takashi Nanya (Univ. of Tokyo)
 [more] SDM2006-128 ICD2006-82
pp.19-24
CPSY, DC 2006-04-14
13:30
Tokyo Takeda Hall [Invited Talk] Dependable Computing --- the past, present and future
Takashi Nanya (Univ. Tokyo)
We review fundamental concepts and established technologies for dependable computing, survey current challenges to assur... [more] CPSY2006-7 DC2006-7
pp.37-42
VLD, ICD, DC, IPSJ-SLDM 2005-11-30
16:35
Fukuoka Kitakyushu International Conference Center A Discussion about Timing Signal Design Considering Delay Variation
Masashi Imai, Kouichi Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. Tokyo)
As the VLSI technology advances, delay variations become extremely
large. There are many factors that cause delay varia... [more]
VLD2005-59 ICD2005-154 DC2005-36
pp.31-36
VLD, ICD, DC, IPSJ-SLDM 2005-11-30
17:00
Fukuoka Kitakyushu International Conference Center Design of High Performance and Low Power Arithmetic Circuits Considering Bit Delay Variation
Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. Tokyo)
As the VLSI technology advances, delay variations will become more serious.
Delay insensitive asynchronous dual-rail ci... [more]
VLD2005-60 ICD2005-155 DC2005-37
pp.37-42
DE, DC 2005-10-17
14:15
Tokyo NTT Musashino R&D center Hopes and Challenges in Research on Dependable Computing -- in combination with a report on DSN2005 --
Takashi Nanya (Univ. Tokyo)
As process technologies decrease in feature size and networks pervade every aspects of modern societies, computer system... [more] DE2005-129 DC2005-23
pp.25-30
 Results 1 - 10 of 10  /   
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