IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
... (for ESS/CS/ES/ISS)
Tech. Rep. Archives
... (for ES/CS)
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 23件中 1~20件目  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, DC, IPSJ-ARC [detail] 2019-07-26
15:20
Hokkaido Kitami Civic Hall Comparison of Compression Techniques for Communication Efficiency in Distributed CNN
Ryuta Shingai, Takashi Nakada, Yasuhiko Nakashima (Naist) CPSY2019-36 DC2019-36
Since the amount of calculation required for the inference processing of the neural network is large, it is processed no... [more] CPSY2019-36 DC2019-36
pp.203-208
DC, CPSY, IPSJ-ARC [detail] 2019-06-11
13:00
Kagoshima National Park Resort Ibusuki CPSY2019-1 DC2019-1  [more] CPSY2019-1 DC2019-1
pp.1-5
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-06
13:50
Hiroshima Satellite Campus Hiroshima
Hiroki Nishimoto, Takashi Nakada, Yasuhiko Nakashima (NAIST) VLD2018-62 DC2018-48
 [more] VLD2018-62 DC2018-48
pp.155-160
CPSY, DC, IPSJ-ARC [detail] 2018-06-15
10:00
Yamagata Takamiya Rurikura Resort CPSY2018-4 DC2018-4  [more] CPSY2018-4 DC2018-4
pp.93-98
CPSY 2017-11-19
15:00
Aomori Aomori Tourist Information Center, ASPAM [Poster Presentation] A Programmable Analog Calculation Unit based on Support Vector Regression
Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPSY2017-55
This work explores an architecture of programmable analog circuitry to calculate arbitrary functions with acceptable acc... [more] CPSY2017-55
pp.27-32
CPSY 2017-11-19
15:00
Aomori Aomori Tourist Information Center, ASPAM [Poster Presentation] Compression and Aggregation for Optimizing Information Transmission in Distributed CNN
Hisakazu Fukuoka, Yuria Hiraga, Takamasa Mitani, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPSY2017-59
 [more] CPSY2017-59
pp.51-54
CPSY, DC, IPSJ-ARC
(Joint) [detail]
2017-07-27
17:30
Akita Akita Atorion-Building (Akita)
Hisakazu Fukuoka, Takamasa Mitani, Yuria Hiraga, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPSY2017-30
(To be available after the conference date) [more] CPSY2017-30
pp.151-155
RECONF, CPSY, DC, IPSJ-ARC
(Joint) [detail]
2017-05-23
14:20
Hokkaido Noboribetsu-Onsen Dai-ichi-Takimoto-Kan A Compact Low-Latency Systematic Successive Cancellation Polar Decoder for Visible Light Communication Systems
Duc Phuc Nguyen, Dinh Dung Le, Thi Hong Tran, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPSY2017-2 DC2017-2
Channel polarization and Polar code are widely considered as major breakthroughs in coding theory because they have show... [more] CPSY2017-2 DC2017-2
pp.3-7
RECONF, CPSY, DC, IPSJ-ARC
(Joint) [detail]
2017-05-24
09:40
Hokkaido Noboribetsu-Onsen Dai-ichi-Takimoto-Kan A Concept for Distributed Neural Network on Edge Computing
Yuria Hiraga, Takamasa Mitani, Hisakazu Fukuoka, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPSY2017-11 DC2017-11
 [more] CPSY2017-11 DC2017-11
pp.62-67
ICD, CPSY 2016-12-15
15:30
Tokyo Tokyo Institute of Technology ICD2016-57 CPSY2016-63 (To be available after the conference date) [more] ICD2016-57 CPSY2016-63
p.33
CPSY, DC
(Joint)
2014-07-30
15:15
Niigata Toki Messe, Niigata Spatiotemporal compression and hierarchization for low-power sensor networks
Takashi Nakada, Yukito Tanaka (Univ. of Tokyo), Keiro Muro (Hitachi), Takeo Murakami, Shintaro Fujisaki (Hitachi Information & Telecommunication Engineering), Takanori Shimura, Taizo Kinoshita (Hitachi), Hiroshi Nakamura (Univ. of Tokyo) CPSY2014-40
Minimizing the energy consumption of sensor network systems is a very critical concern. As a result, we need to minimize... [more] CPSY2014-40
pp.179-184
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2011-11-29
13:25
Miyazaki NewWelCity Miyazaki A Scaling Method for a Large FU Array Accerlator on Multiple FPGAs
Kodai Moritaka, Shunsuke Shitaoka, Kazuhiro Yoshimura, Jun Yao, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPSY2011-44
We proposed previously Linear Array Pipeline Processor (LAPP), which can be used to map an inner
loop of conventional V... [more]
CPSY2011-44
pp.9-14
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2011-11-29
14:40
Miyazaki NewWelCity Miyazaki Implementation of an FU Array Accelerator and its Analysis
Mitsutoshi Saito, Shunsuke Shitaoka, Kazuhiro Yoshimura, Jun Yao, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPM2011-159 ICD2011-91
We have previously proposed Linear Array Pipeline Processor (LAPP), which can map an inner loop of conventional VLIW cod... [more] CPM2011-159 ICD2011-91
pp.53-58
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2011-11-30
10:05
Miyazaki NewWelCity Miyazaki A DMR based Parmanent Error Locating Method for a Dependable FU Array
Yohei Hazama, Jun Yao, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPSY2011-51
Triple Modular Redundancy (TMR) is widely used to locating the erroneous unit inside electronic device when the possibil... [more] CPSY2011-51
pp.47-52
DC, CPSY
(Joint)
2011-07-28
15:15
Kagoshima   Proposal for High Efficient DVS Using Adaptive Redundancy of FUs
Yukihiro Sasagawa, Jun Yao, Takashi Nakada, Yasuhiko Nakashima (NAIST) DC2011-15
Recently, the well-known low power technology DVS(Dynamic Voltage Scaling) is aggressively applied to processors with Ra... [more] DC2011-15
pp.1-6
ICD 2010-12-16
15:10
Tokyo RCAST, Univ. of Tokyo [Poster Presentation] Design of Memory Access Controller for FU Array Accelerator
Shunsuke Shitaoka, Takuya Iwakami, Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima (NAIST) ICD2010-114
Our previously proposed FU (functional unit) array accelerator can achieve both high energy-efficiency and binary-compat... [more] ICD2010-114
pp.95-96
ICD 2010-12-16
15:10
Tokyo RCAST, Univ. of Tokyo [Poster Presentation] Design of An FU Network for Array Accelerators
Suguru Ooue, Takuya Iwakami, Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima (NAIST) ICD2010-115
We have proposed Linear Array Pipeline Processor (LAPP) as a special implementation of Function Unit (FU) array based ac... [more] ICD2010-115
pp.97-99
ICD 2010-12-17
14:15
Tokyo RCAST, Univ. of Tokyo Fine Grained Time Sharing to Extend Capacity of FU Array
Takuya Iwakami, Kazuhiro Yoshimura, Kodai Mori, Takashi Nakada, Yasuhiko Nakashima (NAIST) ICD2010-123
We have proposed Linear Array Pipeline Processor (LAPP) which can map popular VLIW codes onto
FU array and execute them... [more]
ICD2010-123
pp.141-146
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-UBI, IPSJ-MBL [detail] 2010-03-28
11:15
Tokyo   Design and Evaluation of An Instruction Scheduler for FU Array Processor
Kazuhiro Yoshimura, Munehisa Agari, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPSY2009-94 DC2009-91
Recently, we have proposed Linear Array Pipeline Processor (LAPP) that improves energy efficiency for various workloads ... [more] CPSY2009-94 DC2009-91
pp.511-516
CPSY, DC
(Joint)
2009-08-04
- 2009-08-05
Miyagi   An efficient middle-level framework for quantum circuit simulation on multiple simulator platforms
Antti Vikman, Takashi Nakada (NAIST), Masaki Nakanishi (Yamagata Univ.), Shigeru Yamashita (Ritsumeikan Univ.), Yasuhiko Nakashima (NAIST) CPSY2009-14
Simulating of quantum computers is hard task for any classical computer. Even though multiple simulation libraries have ... [more] CPSY2009-14
pp.25-30
 23件中 1~20件目  /  [Next]  
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan