IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
... (for ESS/CS/ES/ISS)
Tech. Rep. Archives
... (for ES/CS)
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 24件中 1~20件目  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS, VLD [detail] 2020-03-04
11:20
Okinawa Okinawa Ken Seinen Kaikan A Study of Arithmetic-Oriented Application Implementations for Via-Switch FPGA
Takashi Imagawa (Ritsumeikan Univ.), Yu Jaehoon (Tokyo Tech), Masanori Hashimoto (Osaka Univ.), Hiroyuki Ochi (Ritsumeikan Univ.) VLD2019-98 HWS2019-71
Via-Switch FPGAs have different features from conventional SRAM-based FPGAs. It is necessary to build the application ci... [more] VLD2019-98 HWS2019-71
pp.25-29
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-14
09:40
Ehime Ehime Prefecture Gender Equality Center Device characteristic measurement for realizing CMOS-compatible non-volatile memory using FiCC
Ippei Tanaka, Naoyuki Miyagawa, Tomoya Kimura, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2019-36 DC2019-60
This report proposes a new non-volatile memory element that can be fabricated with a standard CMOS process, and that can... [more] VLD2019-36 DC2019-60
pp.63-68
SIS 2019-03-06
13:20
Tokyo Tokyo Univ. Science, Katsushika Campus A Study of Low-Energy Video Encoding Method for Raspberry Pi
Atsuki Fukumoto, Takashi Imagawa (Ritsumeikan Univ.), Hiroshi Tsutsui, Yoshikazu Miyanaga (Hokkaido Univ.), Hiroyuki Ochi (Ritsumeikan Univ.) SIS2018-38
In this paper, we consider energy-efficient video encoding methods which are appropriate for performance-, power- and en... [more] SIS2018-38
pp.5-9
SIS 2019-03-07
10:40
Tokyo Tokyo Univ. Science, Katsushika Campus A Study of Global Motion Compensation for Frame Interpolation with High-Resolution and High-Frame Rate Video
Keita Ukihashi, Takashi Imagawa (Ritsumeikan Univ.), Hiroshi Tsutsui, Yoshikazu Miyanaga (Hokkaido Univ.), Hiroyuki Ochi (Ritsumeikan Univ.) SIS2018-47
Frame interpolation is a method to realize wireless transmission of high frame-rate and high-resolution video in a senso... [more] SIS2018-47
pp.53-58
HWS, VLD 2019-02-27
13:05
Okinawa Okinawa Ken Seinen Kaikan Wire Load Model for Power Consumption Evaluation of Via-Switch FPGA
Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2018-97 HWS2018-60
In this report, we consider a wire load model for an FPGA using new nano-device called via-switch to allow power estimat... [more] VLD2018-97 HWS2018-60
pp.25-30
HWS, VLD 2019-02-28
13:05
Okinawa Okinawa Ken Seinen Kaikan High-Speed and Noise-Tolerant High-Radix Tree Domino Adder Targeted to 65 nm FD-SOI Technology
Kazuki Niino, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2018-112 HWS2018-75
Domino logic was introduced at the forefront of the LSI market in the 2000s for high-speed circuits. In recent years, h... [more] VLD2018-112 HWS2018-75
pp.115-120
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-07
09:00
Hiroshima Satellite Campus Hiroshima Design and fabrication of characteristics measurement circuit for CMOS-compatible ultra-low-power non-volatile memory element using FiCC
Ippei Tanaka, Naoyuki Miyagawa, Tomoya Kimura, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2018-65 DC2018-51
This report proposes a new non-volatile memory element that can be fabricated with a standard CMOS process, and that can... [more] VLD2018-65 DC2018-51
pp.183-188
VLD, HWS
(Joint)
2018-02-28
15:00
Okinawa Okinawa Seinen Kaikan A Study on Quality Improvement of Frame Interpolation Method with High-Resolution and High-Frame Rate Video Using Foreground Elimination and Contour Extraction
Hirofumi Ihara, Takashi Imagawa (Ritumeikan Univ), Hiroki Uesaka, Shingo Kokami, Hiroshi Tsutsui, Yoshikazu Miyanaga (Hokkaido Univ), Hiroyuki Ochi (Ritumeikan Univ) VLD2017-98
Frame interpolation is one of methods to realize wireless transmission of high frame-rate and high resolution video unde... [more] VLD2017-98
pp.55-60
IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2018-01-19
11:05
Kanagawa Raiosha, Hiyoshi Campus, Keio University A study on the power efficiency of via-switch oriented programmable logic 0-1-A-~A LUT
Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2017-80 CPSY2017-124 RECONF2017-68
This paper quantitatively shows the superiority of 0-1-$A$-$overline{A}$ LUT to 0-1 LUT in terms of area, delay time and... [more] VLD2017-80 CPSY2017-124 RECONF2017-68
pp.107-112
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-07
09:00
Kumamoto Kumamoto-Kenminkouryukan Parea Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch
Tetsuaki Fujimoto (Ritsumeikan Univ.), Wataru Takahashi, Kazutoshi Wakabayashi (NEC), Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2017-38 DC2017-44
This report proposes an optimal implementation of FFT circuit for mixed grained reconfigurable architecture using via-sw... [more] VLD2017-38 DC2017-44
pp.67-72
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-07
09:25
Kumamoto Kumamoto-Kenminkouryukan Parea Routing method considering programming constraint of reconfigurable device using via-switch crossbars
Kosei Yamaguchi, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2017-39 DC2017-45
This report proposes a new routing method that considers constraint on the programming of switches in the reconfigurable... [more] VLD2017-39 DC2017-45
pp.73-78
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-07
10:55
Kumamoto Kumamoto-Kenminkouryukan Parea A Study of Pipelined Hardware Design of Matrix Inversion for Signal Separation in MIMO-OFDM Wireless Communication
Takashi Imagawa (Ritsumeikan Univ.), Takahiro Ikeshita, Hiroshi Tsutsui, Yoshikazu Miyanaga (Hokkaido Univ.) VLD2017-45 DC2017-51
With the increase in the number of MIMO streams and OFDM subcarriers for high-speed wireless communication, the amount o... [more] VLD2017-45 DC2017-51
pp.105-108
SIP, CAS, MSS, VLD 2017-06-19
10:40
Niigata Niigata University, Ikarashi Campus Placement Algorithm for Mixed-Grained Reconfigurable Architecture with Dedicated Carry Chain
Koki Honda, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) CAS2017-4 VLD2017-7 SIP2017-28 MSS2017-4
This paper proposes a placement algorithm using analytical placement (AP) and low-temperature simulated annealing (SA) f... [more] CAS2017-4 VLD2017-7 SIP2017-28 MSS2017-4
pp.19-24
SIP, CAS, MSS, VLD 2017-06-19
11:00
Niigata Niigata University, Ikarashi Campus Selectable Grained Reconfigurable Architecture (SGRA) and Its Design Automation
Ryosuke Koike, Takashi Imagawa (Ritsumeikan Univ.), Roberto Yusi Omaki (Synthesis), Hiroyuki Ochi (Ritsumeikan Univ.) CAS2017-5 VLD2017-8 SIP2017-29 MSS2017-5
In this paper, we describe a Selectable Grained Reconfigurable Architecture (SGRA) in which each Configurable Logic Bloc... [more] CAS2017-5 VLD2017-8 SIP2017-29 MSS2017-5
pp.25-30
SIP, CAS, MSS, VLD 2017-06-20
15:10
Niigata Niigata University, Ikarashi Campus CMOS-compatible Temperature and Illuminance Sensor for Solar-cell-embedded Chip
Tatsuya Banno, Tomoya Kimura, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) CAS2017-22 VLD2017-25 SIP2017-46 MSS2017-22
This paper proposes a temperature and illuminance sensor circuit that operates with about 0.5 V supply voltage harvested... [more] CAS2017-22 VLD2017-25 SIP2017-46 MSS2017-22
pp.113-118
SIS 2015-12-03
16:40
Fukui Matsuya-sensen (Awara city, Fukui) An Evaluation for Appropriate Camera Selection in 3D Reconstruction System Using Multiple Cameras
Hikaru Aoki, Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga (Hokkaido Univ.) SIS2015-38
In 3D reconstruction using structure from motion (SfM), it is necessary to
capture images of a subject from various vie... [more]
SIS2015-38
pp.53-56
SIS 2015-12-03
17:00
Fukui Matsuya-sensen (Awara city, Fukui) Processing Time Reduction of Iterative Shrinkage Smoothing Using Parallel Processing
Seijiro Imai, Dabwitso Kasauka, Takashi Imagawa, Hiroshi Tsutsui (Hokkaido Univ.), Hiroyuki Okuhata (Synthesis Co.), Yoshikazu Miyanaga (Hokkaido Univ.) SIS2015-39
Iterative shrinkage smoothing algorithm can perform image smoothing with
eliminating fine details and preserving princi... [more]
SIS2015-39
pp.57-60
SIS 2015-12-04
09:50
Fukui Matsuya-sensen (Awara city, Fukui) An Evaluation of High Quality Synchronization Method Based on Delayed and Symmetric Correlation in MIMO-OFDM
Sukeyuki Iwata, Masahito Umehara, Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga (Hokkaido Univ.) SIS2015-42
In this paper, we propose a highly accurate ODFM symbol timing synchronization method using cross–correlation in a... [more] SIS2015-42
pp.73-76
SIS 2015-12-04
11:00
Fukui Matsuya-sensen (Awara city, Fukui) An Accuracy Evaluation of Frame Interpolation Method Using High-Resolution Video and High-Frame Rate Video
Hiroki Uesaka, Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga (Hokkaido Univ.) SIS2015-45
In this paper, we propose a new frame interpolation method using video that
has two types of information; high-resoluti... [more]
SIS2015-45
pp.89-94
SIS 2015-12-04
11:20
Fukui Matsuya-sensen (Awara city, Fukui) Image Shrinking Based Computational Cost Reduction of Moving Area Extraction Using Global Motion Estimation with KLT Tracker and Background Subtraction
Shingo Kokami, Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga (Hokkaido Univ.) SIS2015-46
This paper proposes a computational cost reduction method for moving area
extraction using global motion estimation wit... [more]
SIS2015-46
pp.95-98
 24件中 1~20件目  /  [Next]  
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : 以上の論文すべての著作権はIEICEに帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan