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Committee Date Time Place Paper Title / Authors Abstract Paper #
DC, CPSY 2010-04-13
16:20		 Tokyo   Improvement of Transient-Fault-Tolerant Scheme for Out-of-Order Superscalar Processors
Satoshi Arima, Takashi Okada, Takanobu Kita, Ryota Shioya, Masahiro Goshima, Shuichi Sakai (The Univ. of Tokyo) CPSY2010-5 DC2010-5		 The feature size of LSI is getting smaller year by year, increasing random variation between the elements. To overcome t... [more] CPSY2010-5 DC2010-5
pp.21-26
DC, CPSY 2010-04-13
17:20		 Tokyo   Fault-tolerant FPGA Architecture
Takashi Okada, Takanobu Kita, Ryota Shioya, Masahiro Goshima, Shuichi Sakai (Tokyo Univ.) CPSY2010-7 DC2010-7		 Since electric devices for space applications are likely to experience radiation induced errors, such as the Single Even... [more] CPSY2010-7 DC2010-7
pp.33-37
CPSY, DC
(Joint)		 2009-08-04
- 2009-08-05		 Miyagi   Exploratory evaluation of a clocking scheme with relaxed timing constraint
Takanobu Kita (Univ. of Tokyo), Shou Tarui (Hitachi Ltd.), Ryota Shioya (Univ. of Tokyo/Research Fellowship for Young Scientists DC), Masahiro Goshima, Shuichi Sakai (Univ. of Tokyo) CPSY2009-20		 The feature size of LSI is getting smaller year by year, increasing random variation between the elements. These days, t... [more] CPSY2009-20
pp.61-66
ICD, IPSJ-ARC 2008-05-13
09:30		 Tokyo   Speculation scheme that continues executing mispredicted instructions
Takanobu Kita, Ryota Shioya, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai (Univ. of Tokyo) 		Modern processors are acquiring deeper pipelines as their clock frequencies grow higher,leading to large misprediction p... [more] ICD2008-18
pp.7-12
 Results 1 - 4 of 4  /   
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