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Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM, ED, CPM 2017-05-25
16:15
Aichi VBL, Nagoya University Development of plasmonic retention circuit using bow-tied metallic waveguide
Takahiro Furuki, Masashi Ota, Yuya Ishii, Mitsuo Fukuda (TUT) ED2017-21 CPM2017-7 SDM2017-15
We have numerically demonstrated a plasmonic temporary retention circuit using short range surface plasmon polaritons (S... [more] ED2017-21 CPM2017-7 SDM2017-15
pp.33-37
ED 2016-08-10
11:25
Tokyo Kikai-Shinko-Kaikan Bldg. All-optical logic circuit using plasmonic multimode interference
Masashi Ota, Asahi Sumimura, Ryo Watanabe, Kotaro Nakayama, Takahiro Furuki, Yuya Ishii, Mitsuo Fukuda (Toyohashi Univ. of Tech.) ED2016-41
Plasmonic logic circuits are of interest because of their potential for high-speed information processing and high-densi... [more] ED2016-41
pp.61-64
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