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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, CAS, MSS, SIP | 2012-07-02 14:10 |
Kyoto | Kyoto Research Park | An Evaluation of Heuristic Fault Simulation Algorithms for Transient Faults in Sequential Circuits Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.)  CAS2012-10 VLD2012-20 SIP2012-42 MSS2012-10 |
[more] | CAS2012-10 VLD2012-20 SIP2012-42 MSS2012-10 pp.55-60 |
| VLD | 2012-03-07 10:05 |
Oita | B-con Plaza | An Efficient Method to Analyze Logic Masking Effects of Soft Errors in Sequential Circuits Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) VLD2011-134 |
[more] | VLD2011-134 pp.85-90 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-17 13:50 |
Kanagawa | Keio Univ (Hiyoshi Campus) | A Heuristic Method using CODCs for Extraction of Maximum Observability Don't Care Set Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) VLD2010-91 CPSY2010-46 RECONF2010-60 |
Sets of observability don't cares (ODCs) can be employed for multi-level logic optimization or propagation analysis of p... [more] | VLD2010-91 CPSY2010-46 RECONF2010-60 pp.43-48 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-04 15:40 |
Kochi | Kochi City Culture-Plaza | FlexMerge: A Logic Optimization Technique to Minimize Area for LUT-based FPGAs Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) VLD2009-68 DC2009-55 |
This paper presents a novel logic optimization technique to minimize the number of LUTs for the post-processing of LUT-b... [more] | VLD2009-68 DC2009-55 pp.185-190 |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 14:10 |
Kanagawa | An Efficient Cut Enumeration for Depth-Optimum Technology Mapping for LUT-based FPGAs Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) |
This paper presents a top-down cut enumeration for depth-minimum technology mapping for LUT-based FPGAs. Enumerating all... [more] | VLD2008-101 CPSY2008-63 RECONF2008-65 pp.57-62 |
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| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-22 15:20 |
Fukuoka | Kitakyushu International Conference Center | Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) |
[more] | VLD2007-101 DC2007-56 pp.73-78 |
| RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2006-11-28 11:20 |
Fukuoka | Kitakyushu International Conference Center | Depth-Optimum and Area-Optimal Technology Mapping for LUT-based FPGAs Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) |
[more] | VLD2006-59 DC2006-46 pp.47-52 |
| SIP, ICD, IE, IPSJ-SLDM | 2005-10-21 15:50 |
Miyagi | Ichinobo, Sakunami-Spa | A cell library development methodology for character projection Makoto Sugihara (ISIT), Taiga Takata, Kenta Nakamura (Kyushu Univ.), Ryoichi Inanami (e-BEAM), Hiroaki Hayashi (Tokyo Electron), Katsumi Kishimoto (e-BEAM), Tetsuya Hasebe (Tokyo Electron), Yukihiro Kawano (e-BEAM), Yusuke Matsunaga, Kazuaki Murakami (Kyushu Univ.), Katsuya Okumura (Univ. of Tokyo) |
We propose a cell library development methodology for throughput enhancement of electron beam direct-write (EBDW) system... [more] | SIP2005-128 ICD2005-147 IE2005-92 pp.79-84 |
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