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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 7 of 7  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, HWS
(Joint)
2018-03-01
10:55
Okinawa Okinawa Seinen Kaikan Implementation and Evaluation of MCTS-Based Parallel Prefix Adder Synthesis
Taeko Matsunaga (NBU), Yusuke Matsunaga (Kyushu Univ.)
 [more]
IE, SIP, IPSJ-SLDM 2008-10-07
11:30
Iwate Aiina Center (Morioka) Synthesis of partial product adders on FPGAs
Taeko Matsunaga, Shinji Kimura (Waseda Univ.), Yusuke Matsunaga (Kyushu Univ.)
 [more] SIP2008-117 IE2008-81
pp.59-64
VLD, IPSJ-SLDM 2008-05-08
16:40
Hyogo Kobe Univ. Improvement of swtching activity aware algorithm for prefix graph synthesis
Taeko Matsunaga, Shinji Kimura (Waseda Univ), Yusuke Matsunaga (Kyushu Univ)
 [more] VLD2008-6
pp.31-36
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2007-11-22
13:50
Fukuoka Kitakyushu International Conference Center Parallel prefix adder synthesis based on Ling’s carry computation
Taeko Matsunaga, Shinji Kimura (Waseda Univ.), Yusuke Matsunaga (Kyushu Univ.)
Ling adders calculate carry propagation based on adjacent bit pairs,
and can be formulated as parallel prefix adders. I... [more]
VLD2007-97 DC2007-52
pp.49-54
VLD, IPSJ-SLDM 2007-05-11
11:45
Kyoto Kyodai Kaikan On power-conscious approach for prefix graph synthesis
Taeko Matsunaga (Waseda Univ), Yusuke Matsunaga (Kyushu Univ.)
A prefix graph visualizes a global structure of a parallel prefix
adder at technology independent level. Several approa... [more]
VLD2007-12
pp.31-36
ICD, SIP, IE, IPSJ-SLDM 2006-10-27
09:20
Miyagi   On synthesis algorithm for parallel prefix adders using dynamic programming
Taeko Matsunaga (FLEETS), Yusuke Matsunaga (Kyushu Univ.)
This paper addresses parallel prefix adder synthesis which targets area minimization under given timing constraints. Th... [more] SIP2006-102 ICD2006-128 IE2006-80
pp.7-12
VLD, ICD, DC, IPSJ-SLDM 2005-12-01
14:20
Fukuoka Kitakyushu International Conference Center Consideration on Delay Estimation Methods for Prefix Graphs
Taeko Matsunaga (FLEETS), Yusuke Matsunaga (Kyushu Univ.)
Prefix graph is an abstract representation of a parallel prefix adder and used to compare characteristics of various typ... [more] VLD2005-69 ICD2005-164 DC2005-46
pp.49-54
 Results 1 - 7 of 7  /   
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