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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2009-03-11
16:40		 Okinawa   A Maximization Method of Parallel Wire Lengths in Routing Area With Lengths in Routing Area with Obstacles
Suguru Suehiro, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2008-136		 Due to the speeding up of VLSI systems, the PCB routing design is requested to take signal delay and signal integrity in... [more] VLD2008-136
pp.59-64
CAS 2008-02-01
10:30		 Okinawa   A note of an estimation of the maximum wire length in the area with obstacle
Suguru Suehiro, Yukihide Kohira, Atsushi Takahashi (Tokyo Tech) CAS2007-97		 According to the speeding up of VLSI, the requirement to signal is becoming tighter in order to prevent timing errors. T... [more] CAS2007-97
pp.19-23
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