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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-29 13:25 |
Miyazaki |
NewWelCity Miyazaki |
A Scaling Method for a Large FU Array Accerlator on Multiple FPGAs Kodai Moritaka, Shunsuke Shitaoka, Kazuhiro Yoshimura, Jun Yao, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPSY2011-44 |
We proposed previously Linear Array Pipeline Processor (LAPP), which can be used to map an inner
loop of conventional V... [more] |
CPSY2011-44 pp.9-14 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-29 14:40 |
Miyazaki |
NewWelCity Miyazaki |
Implementation of an FU Array Accelerator and its Analysis Mitsutoshi Saito, Shunsuke Shitaoka, Kazuhiro Yoshimura, Jun Yao, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPM2011-159 ICD2011-91 |
We have previously proposed Linear Array Pipeline Processor (LAPP), which can map an inner loop of conventional VLIW cod... [more] |
CPM2011-159 ICD2011-91 pp.53-58 |
ICD |
2010-12-16 15:10 |
Tokyo |
RCAST, Univ. of Tokyo |
[Poster Presentation]
Design of Memory Access Controller for FU Array Accelerator Shunsuke Shitaoka, Takuya Iwakami, Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima (NAIST) ICD2010-114 |
Our previously proposed FU (functional unit) array accelerator can achieve both high energy-efficiency and binary-compat... [more] |
ICD2010-114 pp.95-96 |
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