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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2014-01-28 15:00 |
Kyoto | Kyoto Univ. Tokeidai Kinenkan | [Poster Presentation]
An Autonomous Control Cache Memory for Dynamic Variation Tolerance with Bit-Enhancing Memory Yuta Kimi, Yohei Nakata, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa (Kobe Univ.), Makoto Nagata (Kobe Univ./JST CREST), Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai (Renesas Electronics Corporation), Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST CREST)  ICD2013-125 |
Processor reliability is getting more critical issue since technology scaling degrades processor tolerance against power... [more] | ICD2013-125 p.59 |
| ICD | 2012-12-17 15:55 |
Tokyo | Tokyo Tech Front | [Poster Presentation]
Low-Power Ferroelectric 6T4C Shadow SRAM for Normally-Off Computing Tomoki Nakagawa, Shusuke Yoshimoto, Yuki Kitahara, Koji Yanagida, Yohei Umeki, Shunsuke Okumura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2012-98 |
In recent years, sensor network has attracted much attention in agricultural, medical, and disaster-prevention area to c... [more] | ICD2012-98 p.41 |
| ICD, SDM | 2012-08-02 09:10 |
Hokkaido | Sapporo Center for Gender Equality, Sapporo, Hokkaido | A Variation-Aware Low-Voltage Set-Associative Cache with Mixed-Associativity Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) SDM2012-63 ICD2012-31 |
In this paper, we propose the mixed associativity scheme using 7T/14T SRAM, which can reduce the minimum operating volta... [more] | SDM2012-63 ICD2012-31 pp.1-6 |
| ICD, SDM | 2012-08-02 09:35 |
Hokkaido | Sapporo Center for Gender Equality, Sapporo, Hokkaido | A 40-nm 256-Kb Sub-10 pJ/Access 8T SRAM with Read Bitline Amplitude Limiting (RBAL) Scheme Shusuke Yoshimoto, Masaharu Terada, Yohei Umeki, Shunsuke Okumura (Kobe Univ.), Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano (STARC), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) SDM2012-64 ICD2012-32 |
[more] | SDM2012-64 ICD2012-32 pp.7-12 |
| ICD | 2012-04-24 14:15 |
Iwate | Seion-so, Tsunagi Hot Spring (Iwate) | A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura (Kobe Univ.), Toshikazu Suzuki, Shinji Miyano (STARC), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2012-14 |
This paper presents a novel disturb mitigation scheme which achieves low-power and low-voltage operation for a deep sub-... [more] | ICD2012-14 pp.73-78 |
| ICD | 2012-04-24 15:15 |
Iwate | Seion-so, Tsunagi Hot Spring (Iwate) | Low-Energy Block-Level Instantaneous Comparison 7T SRAM for Dual Modular Redundancy Yohei Umeki, Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST) ICD2012-16 |
This paper proposes a 7T SRAM that realizes a block-level instantaneous comparison feature. The proposed SRAM is useful ... [more] | ICD2012-16 pp.85-90 |
| ICD | 2012-04-24 16:05 |
Iwate | Seion-so, Tsunagi Hot Spring (Iwate) | A 128-bit Chip Identification Generating Scheme Exploiting SRAM Bitcells with Failure Rate of 4.45X 10-19 Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ., JST CREST) ICD2012-18 |
We propose a chip identification (ID) generating scheme with random variation of transistor characteristics in SRAM bitc... [more] | ICD2012-18 pp.97-102 |
| ICD, IPSJ-ARC | 2012-01-20 10:30 |
Tokyo | Associativity-Variable Cache to Adaptively Expand Operating Voltage Margin Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (JST) ICD2011-139 |
This paper presents a dependable cache memory for which associativity can be reconfigured dynamically. The proposed asso... [more] | ICD2011-139 pp.55-60 |
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| ICD | 2011-12-16 14:25 |
Osaka | 0.42-V 576-kb 0.15-um FD-SOI SRAM with 7T/14T Bit Cells and Substrate Bias Control Circuits for Intra-Die and Inter-Die Variability Compensation Shusuke Yoshimoto, Kosuke Yamaguchi, Shunsuke Okumura, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.) ICD2011-133 |
We propose 7T/14T FD-SOI SRAM with a substrate bias control mechanism. The 14T configuration suppresses intra-die variat... [more] | ICD2011-133 pp.155-160 |
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| CPSY | 2011-10-21 09:30 |
Hyogo | Dependability evaluation of processor using the dependable SRAM by system-level fault injection Yusuke Takeuchi, Yohei Nakata (Kobe Univ.), Yasuhiro Ito, Yasuo Sugure, Shigeru Oho (Hitachi), Shunsuke Okumura, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST) CPSY2011-25 |
We propose a fault-injection system (FIS) that can inject faults such as read/write margin failures and soft errors into... [more] | CPSY2011-25 pp.1-6 |
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| ICD | 2011-04-19 09:30 |
Hyogo | Kobe University Takigawa Memorial Hall | 0.45-V Operating Vt-Variation Tolerant 9T/18T Dual-Port SRAM Koji Yanagida, Hiroki Noguchi, Shunsuke Okumura, Tomoya Takagi, Koji Kugata (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST), Hiroshi Kawaguchi (Kobe Univ.) ICD2011-8 |
We proposes a dependable dual-port SRAM with 9T/18T bitcell structure. The proposed SRAM has two operating modes: a 9T n... [more] | ICD2011-8 pp.43-48 |
| IPSJ-SLDM, SIP, IE, ICD [detail] | 2010-10-05 14:00 |
Chiba | Makuhari Messe, International Conference Hall | 7T SRAM Enabling Low-Energy Simultaneous Block Copy Shunsuke Okumura, Yuki Kagiyama, Shusuke Yoshimoto, Kosuke Yamaguchi, Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) SIP2010-57 ICD2010-71 IE2010-75 |
This paper proposes 7T SRAM which realizes block level simultaneous copying feature. The proposed SRAM can be used for d... [more] | SIP2010-57 ICD2010-71 IE2010-75 pp.49-54 |
| ICD | 2009-04-14 10:40 |
Miyagi | Daikanso (Matsushima, Miyagi) | A 0.56-V 128kb 10T SRAM Using Column Line Assist (CLA) Scheme Shusuke Yoshimoto, Yusuke Iguchi, Shunsuke Okumura, Hidehiro Fujiwara, Hiroki Noguchi (Kobe Univ.), Koji Nii (Renesas Technology Corp.), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2009-6 |
We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster a... [more] | ICD2009-6 pp.27-32 |
| ICD | 2009-04-14 11:05 |
Miyagi | Daikanso (Matsushima, Miyagi) | A 7T/14T Dependable SRAM and Its Array Structure to Avoid Half Selection Shunsuke Okumura, Hidehiro Fujiwara, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST-CREST) ICD2009-7 |
We propose a novel dependable SRAM with 7T cells and their array structure that avoids a half-selection problem. The dep... [more] | ICD2009-7 pp.33-38 |
| VLD, IPSJ-SLDM | 2008-05-09 14:35 |
Hyogo | Kobe Univ. | A Dependable SRAM with high-reliability mode and high-speed mode. Shunsuke Okumura, Hidehiro Fujiwara, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) |
We propose a novel dependable SRAM with 7T memory cell pair, and introduce a new concept, “quality of a bit （QoB）” for i... [more] | VLD2008-12 pp.31-36 |
| ICD, ITE-IST | 2007-07-26 17:30 |
Hyogo | A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing Shunsuke Okumura, Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita (Kobe Univ.), Koji Nii (Kobe Univ./Renesas Technology), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2007-53 |
We propose a low-power non-precharge-type two-port SRAM for video processing. The proposed memory cell (MC) has ten tran... [more] | ICD2007-53 pp.95-100 |
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