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Committee Date Time Place Paper Title / Authors Abstract Paper #
MSS, CAS, IPSJ-AL [detail] 2016-11-25
12:55		 Hyogo Kobe Institute of Computing Formal Description of Synchronization by Functional Definition of Synchronous Circuits
Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ.) CAS2016-73 MSS2016-53		 Synchronous circuits are usually defined as D-Flipflop (D-FF) synchronized circuits, but it is doubtful that D-FF comple... [more] CAS2016-73 MSS2016-53
pp.99-104
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2014-11-26
10:45		 Oita B-ConPlaza A hardware description method and sematics providing a timing constrant
Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ.) VLD2014-82 DC2014-36		 Formal verification methods are wide-spreading due to its mathmatical rigorousaspect, although they limited to synchroun... [more] VLD2014-82 DC2014-36
pp.81-86
RECONF 2014-09-19
14:40		 Hiroshima   Formal Verification System of Multi-clock Synchronous Circuits on Multimodal Logic
Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-33		 Regardless of wide using of a formal verification methods, almost all of the methods limited to single-clock synchrounou... [more] RECONF2014-33
pp.93-98
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