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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
ASN 2018-01-31
Oita Yufugo-kan (Oita) A group-based scheduling method for landslide detection system with high-density wireless sensor networks
Shota Ishihara, Masafumi Hashimoto, Naoki Wakamiya, Masayuki Murata (Osaka University), Yasutaka Kawamoto (OKI) ASN2017-97
In this report, we propose a group-based scheduling method in high-density wireless sensor networks for detection of lan... [more] ASN2017-97
ICD, IPSJ-ARC 2012-01-20
Tokyo   An Evaluation of An FPGA Based on Synchronous/Asynchronous Hybrid Architecture
Yoshiya Komatsu, Masanori Hariyama, Shota Ishihara, Ryoto Tsuchiya, Michitaka Kameyama (Tohoku Univ.) ICD2011-142
This paper presents an FPGA architecture that combines synchronous and asynchronous architectures. Datapath components s... [more] ICD2011-142
RECONF 2010-09-17
Shizuoka Shizuoka University (Faculty of Eng., Hall 2) Structure of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture
Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2010-33
Asynchronous circuit is power-efficient for low-workload sub-circuits since there is no power consumption of the clock t... [more] RECONF2010-33
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-27
Kanagawa Keio Univ (Hiyoshi Campus) Architecture of a Low-Power FPGA Based on Self-Adaptive Voltage Control
Shota Ishihara, Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) VLD2009-84 CPSY2009-66 RECONF2009-69
This paper presents a low-power FPGA with multiple supply voltages. In the proposed FPGA, the supply voltage of each log... [more] VLD2009-84 CPSY2009-66 RECONF2009-69
RECONF 2009-09-18
Tochigi Utsunomiya Univ. An Asynchronous FPGA Using LEDR/4-Phase-Dual-Rail Protocol Converters
Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2009-36
This paper presents an asynchronous FPGA that combines the 4-phase dual-rail encoding and the Level-Encoded Dual-Rail (L... [more] RECONF2009-36
ICD, IPSJ-ARC, IPSJ-EMB 2009-01-14
Osaka Shoushin Kaikan A Low-Power Feild-Programmable VLSI Based on Autonomous Fine-Grain Power-Gating
Masanori Hariyama, Shota Ishihara, Michitaka Kameyama (Tohoku Univ.) ICD2008-138
This paper presents a field-programmable VLSI(FPVLSI) based on fine-grain power gating with small overheads. The asynchr... [more] ICD2008-138
ICD, IPSJ-ARC 2008-05-14
Tokyo   Design of a Multi-Context Field-Programmable VLSI Using Ferroelectric-Based Functional Pass-Gates
Noriaki Idobata, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) ICD2008-28
Multi-Context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching betw... [more] ICD2008-28
ICD, ITE-CE 2007-12-14
Kochi   A Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture
Masanori Hariyama, Shota Ishihara, Michitaka Kameyama (Tohoku Univ.) ICD2007-134
This paper presents a novel asynchronous architecture
of Field-programmable gate arrays (FPGAs) to reduce
the power co... [more]
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