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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 23件中 1~20件目  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, HWS
(Joint)
2018-03-01
15:20
Okinawa Okinawa Seinen Kaikan Hardware/Software co-design environment in model-based parallelization (MBP)
Kazuki Kashiwabara, Shinya Honda, Masato Edahiro (Nagoya Univ.)
In recent years, while the complexity and high performance of in-vehicle systems are progressing, restrictions on time a... [more] VLD2017-115
pp.157-162
VLD, HWS
(Joint)
2018-03-01
16:00
Okinawa Okinawa Seinen Kaikan A C Description Approach for High Level Synthesis to Configure DNN Inference Circuit
Takuya Okamoto, Ryota Yamamoto, Shinya Honda (Nagoya Univ.)
Today, Deep Neural Network (DNN) is utilized in various fields. There is a demand for deep learning in the field of embedd... [more] VLD2017-116
pp.163-168
VLD, HWS
(Joint)
2018-03-01
16:25
Okinawa Okinawa Seinen Kaikan A Concept of DNN Framework for Embedded System Using FPGA
Ryota Yamamoto, Takuya Okamoto, Shinya Honda (Nagoya Univ.), Qian Zhao, Toki Matsumoto, Yukikazu Nakamoto (Hyogo Univ.), Tamotsu Sakai, Tetsuya Aoyama, Kazutoshi Wakabayashi (NEC)
Recently, a DNN (Deep Neural Network) is used in many areas, and it required a field of an embedded system.
For an em... [more]
VLD2017-117
pp.169-174
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-03
13:45
Nagasaki Nagasaki Kinro Fukushi Kaikan Fast and Accurate Estimation of Execution Cycles for ARM Architecture
Go Sato, Yuki Ando, Hiroaki Takada, Shinya Honda, Yutaka Matsubara (Nagoya Univ)
(To be available after the conference date) [more] VLD2015-73 DC2015-69
pp.231-236
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-28
08:55
Kagoshima   System-level design method considering the interrupt processing
Yuki Ando, Yukihito Ishida, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ.)
We propose a system level design methodology for control systems that have both input and output by abstraction of inter... [more] VLD2013-77 DC2013-43
pp.119-124
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-28
10:25
Kagoshima   Automatic synthesis of the inter-processor communication implimentation for hetero multiprocessor systems
Yukihito Ishida, Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ.)
This paper introduces an automatic synthesis technique of inter-processor communication for System-on-chip with heteroge... [more] RECONF2013-50
pp.63-68
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-17
13:25
Kanagawa   A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs
Krzysztof Jozwik, Shinya Honda, Masato Edahiro (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.)
Dynamically Partially Reconfigurable (DPR) FPGAs allow for implementation of a concept of SW-HW multitasking where flow ... [more] VLD2012-130 CPSY2012-79 RECONF2012-84
pp.135-140
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-26
10:30
Fukuoka Centennial Hall Kyushu University School of Medicine Automated Identification of Performance Bottleneck on Embedded Systems for Architecture Exploration
Yuki Ando (Nagoya Univ.), Seiya Shibata (NEC), Shinya Honda (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.)
This paper presents a method to identify performance bottleneck on an embedded systems. At the same time, our method exp... [more] VLD2012-62 DC2012-28
pp.19-24
RECONF 2012-05-29
16:45
Okinawa Tiruru (Naha Okinawa, Japan) Implementation and evaluation of the AES/ADPCM on STP and FPGA with Behavioral Synthesis
Yukihito Ishida, Seiya Shibata, Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ)
Reconfigurable techniques are attracting attention as an alternative to dedicated hardware of SoC.
We have evaluated FP... [more]
RECONF2012-14
pp.77-82
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2011-11-29
09:00
Miyazaki NewWelCity Miyazaki Synthesis of efficient data fetch mechanism from the high level communication description
Masato Minato, Yuki Ando, Seiya Shibata (Nagoya Univ.), Tomoo Kinoshita (Soliton Systems), Shinya Honda, Hiroaki Takada (Nagoya Univ.)
This paper presents efficient data fetch mechanism for the FIFO-based implementation generated by SystemBuilder, a syste... [more] VLD2011-67 DC2011-43
pp.91-96
RECONF 2011-09-26
15:30
Aichi Nagoya Univ. Preemptive Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs - Hardware and Reconfiguration Layers
Krzysztof Jozwik, Shinya Honda (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.)
Preemption techniques for HW (hardware) tasks
have been studied in order to improve their responsiveness
and to allow ... [more]
RECONF2011-29
pp.43-48
RECONF 2011-09-27
09:00
Aichi Nagoya Univ. Case Studies on an FPGA with System-Level Multiprocessor Design Toolset
Seiya Shibata, Yuki Ando, Shinya Honda (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.)
This paper presents a system-level multiprocessor design toolkit: SystemBuilder. SystemBuilder enables system designers... [more] RECONF2011-32
pp.57-62
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-27
10:25
Kanagawa Keio Univ (Hiyoshi Campus) Effective Hardware Task Context Switching in Virtex-4 FPGAs
Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada (Nagoya Univ.)
A unique aspect of flexibility provided by some of the FPGAs such as Xilinx Virtex-4 family is the capability of dynamic... [more] VLD2009-87 CPSY2009-69 RECONF2009-72
pp.113-118
DC, CPSY, IPSJ-SLDM, IPSJ-EMB 2009-03-06
11:15
Niigata Sado Island Integrated Development Center Development of Visualization Tool for Trace Log
Junji Goto, Shinya Honda, Takuya Nagao, Hiroaki Takada (Nagoya Univ.)
 [more] CPSY2008-100 DC2008-91
pp.73-78
DC, CPSY, IPSJ-SLDM, IPSJ-EMB 2008-03-27
09:30
Kagoshima   Function and Efficiency Enhancement of A Simulation Environment with Multiprocessor RTOS
Hiroshi Aiba, Seiya Shibata, Takashi Furukawa, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ.)
This paper presents two improvement techniques which we have applied for our multiprocessor simulation environment with ... [more] DC2007-86 CPSY2007-82
pp.13-18
DC, CPSY, IPSJ-SLDM, IPSJ-EMB 2008-03-27
11:15
Kagoshima   Partitioning Behavioral Descriptions Exploiting Function-Level Parallelism
Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii (Nagoya Univ.)
This paper proposes a method to efficiently generate hardware from a large behavioral description by behavioral synthesi... [more] DC2007-90 CPSY2007-86
pp.37-42
DC, CPSY, IPSJ-SLDM, IPSJ-EMB 2008-03-27
13:20
Kagoshima   A Networking Mechanism for Automotive Sensors
Tomoyuki Kawai, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ.), Hideaki Ishihara, Kyouichi Suzuki, Yoshinori Teshima, Toshihiko Matsuoka, Kenji Yamada (DENSO)
In this paper, we have proposed a hardware mechanism which is useful to meet real-time constraints in the automotive sys... [more] DC2007-93 CPSY2007-89
pp.55-60
DC, CPSY, IPSJ-SLDM, IPSJ-EMB 2008-03-28
14:20
Kagoshima   An Efficient Real-Time Scheduling Algorithm for Temporal Protection with Task's Priority
Yutaka Matsubara, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ.)
In this paper, we propose an efficient scheduling algorithm for
integration of real-time applications in a single proc... [more]
DC2007-113 CPSY2007-109
pp.173-178
VLD, ICD 2008-03-06
14:40
Okinawa TiRuRu A Case Study on MPEG4 Decoder Design with SystemBuilder
Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ.)
This paper presents a case study on designing an MPEG4 decoder system using our system-level design environment named Sy... [more] VLD2007-151 ICD2007-174
pp.43-48
CS 2008-01-28
13:50
Kagoshima Amami-Oshima Island Bit Loading Algorithms Synchronized with Commercial Power Supply on In-home Power Line Multicarrier Communications
Shinya Honda, Daisuke Umehara, Satoshi Denno, Masahiro Morikura (Kyoto Univ.)
In-home PLC (Power Line Communicaiton) is one of the most attractive in-home networkings.
However, there are a lot of t... [more]
CS2007-62
pp.43-48
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