Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
SDM |
2020-01-28 14:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
[Invited Talk]
Performance Maximization of In-Memory Reinforcement Learning with Variability-Controlled Hf1-xZrxO2 Ferroelectric Tunnel Junctions Kensuke Ota, Marina Yamaguchi (kioxia), Radu Berdan, Takao Marukame, Yoshifumi Nishi (Toshiba), Kazuhiro Matsuo, Kota Takahashi, Yuta Kamiya, Shinji Miyano, Jun Deguchi, Shosuke Fujii, Masumi Saitoh (kioxia) SDM2019-84 |
We develop strategies to maximize the performance and reliability of in-memory reinforcement learning with Hf1-xZrxO2 fe... [more] |
SDM2019-84 p.9 |
SDM, ICD |
2015-08-24 10:55 |
Kumamoto |
Kumamoto City |
[Invited Talk]
Implementation of TFET Spice Model for Ultra-Low Power Circuit Analysis Chika Tanaka, Akira Hokazono, Kanna Adachi, Masakazu Goto, Yoshiyuki Kondo, Emiko Sugizaki, Motohiko Fujimatsu, Hiroyuki Hara, Shinji Miyano, Keiichi Kushida, Shigeru Kawanaka (Toshiba) SDM2015-59 ICD2015-28 |
[more] |
SDM2015-59 ICD2015-28 pp.11-13 |
ICD |
2014-04-18 10:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
[Invited Talk]
A 7ns-Access-Time 25μW/MHz 128kb SRAM for Low-Power Fast Wake-Up MCU in 65nm CMOS with 27fA/b Retention Current Toshikazu Fukuda, Koji Kohara, Toshiaki Dozaka, Yasuhisa Takeyama, Tsuyoshi Midorikawa (Toshiba), Kenji Hashimoto, Ichiro Wakiyama (TOSMEC), Shinji Miyano, Takehiko Hojo (Toshiba) ICD2014-12 |
Low leakage 128kb SRAM with 65 nm technology that consumes only 3.5nA (27fA/b) in the retention mode is fabricated. Oper... [more] |
ICD2014-12 pp.59-64 |
SDM, ICD |
2013-08-02 09:00 |
Ishikawa |
Kanazawa University |
SRAM Cell Stability Parameter: Noise Margin or Vmin? Anil Kumar, Takuya Saraya (Univ. of Tokyo), Shinji Miyano (STARC), Toshiro Hiramoto (Univ. of Tokyo) SDM2013-74 ICD2013-56 |
This paper reports the comprehensive analysis of the stability parameter of SRAM cells. Results show that even if noise ... [more] |
SDM2013-74 ICD2013-56 pp.43-46 |
ICD |
2013-04-12 14:45 |
Ibaraki |
Advanced Industrial Science and Technology (AIST) |
[Invited Lecture]
A 13.8pJ/Access/Mbit SRAM with Charge Collector Circuits for Effective Use of Non-Selected Bit Line Charges Shinichi Moriwaki, Yasue Yamamoto, Toshikazu Suzuki (STARC), Atsushi Kawasumi (Toshiba), Shinji Miyano, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. Tokyo) ICD2013-20 |
1Mb SRAM with charge collector circuits for effective use of non-selected bit line charges has been fabricated in 40nm t... [more] |
ICD2013-20 pp.103-108 |
ICD |
2012-12-17 15:55 |
Tokyo |
Tokyo Tech Front |
[Poster Presentation]
Near Threshold Voltage Word-Line Voltage Injection Scheme for Self-Convergence of Threshold Voltage Variation in Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM Daisuke Kobayashi, Kousuke Miyaji (Chuo Univ.), Shinji Miyano (STARC), Ken Takeuchi (Chuo Univ.) ICD2012-94 |
In order to repair the reduction of read margin by the variation of threshold voltage VTH in 6T-SRAM, a unique scheme th... [more] |
ICD2012-94 p.31 |
ICD, SDM |
2012-08-02 09:35 |
Hokkaido |
Sapporo Center for Gender Equality, Sapporo, Hokkaido |
A 40-nm 256-Kb Sub-10 pJ/Access 8T SRAM with Read Bitline Amplitude Limiting (RBAL) Scheme Shusuke Yoshimoto, Masaharu Terada, Yohei Umeki, Shunsuke Okumura (Kobe Univ.), Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano (STARC), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) SDM2012-64 ICD2012-32 |
[more] |
SDM2012-64 ICD2012-32 pp.7-12 |
ICD, SDM |
2012-08-02 10:00 |
Hokkaido |
Sapporo Center for Gender Equality, Sapporo, Hokkaido |
Self-Improvement of Cell Stability in SRAM by Post Fabrication Technique Anil Kumar, Takuya Saraya (Univ. of Tokyo), Shinji Miyano (STARC), Toshiro Hiramoto (Univ. of Tokyo) SDM2012-65 ICD2012-33 |
The post fabrication technique for self-improvement of SRAM cell stability is validated by experiment using 1k DMA SRAM ... [more] |
SDM2012-65 ICD2012-33 pp.13-16 |
SDM, ED (Workshop) |
2012-06-29 12:00 |
Okinawa |
Okinawa Seinen-kaikan |
Reliability Measurement of PFETs under Post Fabrication Self-Improvement Scheme for SRAM Nurul Ezaila Alias, Anil Kumar, Takuya Saraya (Univ. of Tokyo), Shinji Miyano (STARC), Toshiro Hiramoto (Univ. of Tokyo) |
The negative bias temperature instability (NBTI) reliability of PFETs is measured under the post fabrication SRAM self-i... [more] |
|
ICD |
2012-04-23 17:00 |
Iwate |
Seion-so, Tsunagi Hot Spring (Iwate) |
[Panel Discussion]
Thinking of Reconstruction of Japan Semiconductor Indutory in Iwate Shinji Miyano (STARC), Atsushi Sasaki (Iwate Prefecture), Motoyuki Oishi (Nihon Keizai Shimbun,Inc.), Shoun Matsunaga (Tohoku University), Ken Takeuchi (Chuo Univ.), Hiroshi Sukegawa (Toshiba) ICD2012-6 |
[more] |
ICD2012-6 p.29 |
ICD |
2012-04-24 13:00 |
Iwate |
Seion-so, Tsunagi Hot Spring (Iwate) |
[Invited Talk]
57% Faster Read, 31% Lower Read Energy, 256-Times Faster Injection 6T-SRAM with a Carrier-Injection Scheme to Pinpoint and Repair Disturb Fails Kousuke Miyaji (Univ. of Tokyo), Toshikazu Suzuki (Panasonic), Shinji Miyano (STARC), Ken Takeuchi (Univ. of Tokyo) ICD2012-12 |
[more] |
ICD2012-12 pp.61-66 |
ICD |
2012-04-24 13:50 |
Iwate |
Seion-so, Tsunagi Hot Spring (Iwate) |
0.4V SRAM with Bit Line Swing Suppression Charge Share Hierarchical Bit Line Scheme Shinichi Moriwaki, Atsushi Kawasumi (STARC), Toshikazu Suzuki (Panasonic), Yasue Yamamoto, Shinji Miyano, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. of Tokyo) ICD2012-13 |
[more] |
ICD2012-13 pp.67-71 |
ICD |
2012-04-24 14:15 |
Iwate |
Seion-so, Tsunagi Hot Spring (Iwate) |
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura (Kobe Univ.), Toshikazu Suzuki, Shinji Miyano (STARC), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2012-14 |
This paper presents a novel disturb mitigation scheme which achieves low-power and low-voltage operation for a deep sub-... [more] |
ICD2012-14 pp.73-78 |
ICD |
2011-04-19 11:20 |
Hyogo |
Kobe University Takigawa Memorial Hall |
0.5-V, 5.5-nsec Access Time, Bulk-CMOS 8T SRAM with Suspended Bit-Line Read Scheme Toshikazu Suzuki, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara (STARC) ICD2011-12 |
A low-voltage high-speed bulk-CMOS 8T SRAM is proposed. A novel 8-transistor (8T) memory cell with a complementary read ... [more] |
ICD2011-12 pp.65-70 |
ICD |
2011-04-19 11:45 |
Hyogo |
Kobe University Takigawa Memorial Hall |
Suppress of Half Select Disturb in 8T-SRAM by Local Injected Electron Asymmetric Pass Gate Transistor Kousuke Miyaji, Kentaro Honda, Shuhei Tanakamaru (Univ. of Tokyo), Shinji Miyano (STARC), Ken Takeuchi (Univ. of Tokyo) ICD2011-13 |
8T-SRAM cell with asymmetric pass gate transistor by local electron injection is proposed to solve half select disturb. ... [more] |
ICD2011-13 pp.71-76 |
ICD |
2010-12-16 09:30 |
Tokyo |
RCAST, Univ. of Tokyo |
Elimination of Half Select Disturb in 8T-SRAM by Local Injected Electron Asymmetric Pass Gate Transistor Kentaro Honda, Kousuke Miyaji, Shuhei Tanakamaru (Univ. of Tokyo), Shinji Miyano (STARC), Ken Takeuchi (Univ. of Tokyo) ICD2010-95 |
8T-SRAM cell with asymmetric pass gate transistor by local electron injection is proposed to solve half select disturb. ... [more] |
ICD2010-95 pp.1-6 |
ICD |
2010-12-17 13:50 |
Tokyo |
RCAST, Univ. of Tokyo |
Misleading Energy and Performance Claims in Sub/Near Threshold Digital Systems Yu Pu, Xin Zhang, Jim Huang (Univ. of Tokyo), Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano (STARC), Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo) ICD2010-122 |
Many of us in the field of ultra-low-Vdd processors experience difficulty in assessing the sub/near threshold circuit te... [more] |
ICD2010-122 pp.135-140 |
ICD, SDM |
2010-08-27 13:45 |
Hokkaido |
Sapporo Center for Gender Equality |
70% Read Margin Enhancement by VTH Mismatch Self-Repair in 6T-SRAM with Asymmetric Pass Gate Transistor by Zero Additional Cost, Post-Process, Local Electron Injection Kousuke Miyaji, Shuhei Tanakamaru, Kentaro Honda (Univ. of Tokyo), Shinji Miyano (STARC), Ken Takeuchi (Univ. of Tokyo) SDM2010-145 ICD2010-60 |
A VTH mismatch self-repair scheme in 6T-SRAM with asymmetric PG transistor by post-process local electron injection is p... [more] |
SDM2010-145 ICD2010-60 pp.115-120 |
SDM |
2010-06-22 15:15 |
Tokyo |
An401・402 Inst. Indus. Sci., The Univ. of Tokyo |
70% Read Margin Enhancement by VTH Mismatch Self-Repair in 6T-SRAM with Asymmetric Pass Gate Transistor by Zero Additional Cost, Post-Process, Local Electron Injection Kousuke Miyaji, Shuhei Tanakamaru, Kentaro Honda (Univ. of Tokyo), Shinji Miyano (STARC), Ken Takeuchi (Univ. of Tokyo) SDM2010-44 |
A VTH mismatch self-repair scheme in 6T-SRAM with asymmetric PG transistor by post-process local electron injection is p... [more] |
SDM2010-44 pp.61-65 |
ICD |
2009-04-13 15:40 |
Miyagi |
Daikanso (Matsushima, Miyagi) |
[Panel Discussion]
Which memory technology win win the low-VDD race in SoC? Hideto Hidaka (Renesas Tech.), Masanao Yamaoka (Hitachi, Ltd.), Shinji Miyano (Toshiba Corp.), Satoru Akiyama (Hitachi, Ltd.), Tadahiko Sugibayashi (NEC), Syoichiro Kawashima (Fujitsu Limited), Masataka Osaka (Panasonic) ICD2009-4 |
A panel discussion session will high-light low-voltage memory trends, limitations, and future prospects by discussing on... [more] |
ICD2009-4 p.19 |