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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-07 14:10 |
Hiroshima | Satellite Campus Hiroshima | Process Variation-aware Model-based OPC using 0-1 Quadratic Programming Rina Azuma, Yukihide Kohira (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama, Shigeki Nojima (TMC)  VLD2018-70 DC2018-56 |
Due to continuous shrinking of Critical Dimensions (CD) of layout pattern in VLSI, advances of manufacturing process in ... [more] | VLD2018-70 DC2018-56 pp.209-214 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 10:30 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Accurate Lithography Simulation Model based on Deep Learning Yuki Watanabe, Tetsuaki Matsunawa, Taiki Kimura, Shigeki Nojima (Toshiba) VLD2016-56 DC2016-50 |
Lithography simulation is an indispensable technology for today's semiconductor manufacturing processes. To achieve accu... [more] | VLD2016-56 DC2016-50 pp.73-78 |
| VLD, IPSJ-SLDM | 2014-05-29 11:30 |
Fukuoka | Kitakyushu International Conference Center | LELECUT Triple Patterning Lithography Layout Decomposition using Positive Semidefinite Relaxation Yukihide Kohira (Univ. of Aizu), Tomomi Matsui (Tokyo Tech), Yoko Yokoyama, Chikaaki Kodama (Toshiba), Atsushi Takahashi (Tokyo Tech), Shigeki Nojima, Satoshi Tanaka (Toshiba) VLD2014-6 |
One of the most promising techniques in the 14 nm logic node and beyond is triple patterning lithography (TPL). Recently... [more] | VLD2014-6 pp.27-32 |
| VLD | 2014-03-04 14:40 |
Okinawa | Okinawa Seinen Kaikan | Self-Aligned Double and Quadruple Patterning-Aware Grid Routing Chikaaki Kodama (Toshiba), Hirotaka Ichikawa (Toshiba Microelectronics), Fumiharu Nakajima, Koichi Nakayama, Shigeki Nojima, Toshiya Kotani (Toshiba) VLD2013-151 |
Self-Aligned Double and Quadruple Patterning (SADP, SAQP) are leading candidates for sub-$20~nm$ and sub-$14~nm$ node an... [more] | VLD2013-151 pp.99-104 |
| VLD | 2014-03-04 15:05 |
Okinawa | Okinawa Seinen Kaikan | Exposure source optimization by clustering for lithography Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.), Takaki Hashimoto, Keishi Sakanushi, Shigeki Nojima, Toshiya Kotani (Toshiba) VLD2013-152 |
In lithography, we generate patterns on a wafer through a photomask, where patterns generated have to be close to ideal... [more] |
VLD2013-152 pp.105-110 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-29 13:00 |
Miyazaki | NewWelCity Miyazaki | Layout Methodology for Self-Alinged Double Patterning Chikaaki Kodama, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Shoji Mimotogi, Shinji Miyamoto (Toshiba) VLD2011-76 DC2011-52 |
We propose a new layout method for the damascene process of self-aligned double patterning (SADP). In this method, w... [more] |
VLD2011-76 DC2011-52 pp.141-146 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-29 17:00 |
Miyazaki | NewWelCity Miyazaki | [Keynote Address]
Lithography : past, present, and future Shigeki Nojima (Toshiba) VLD2011-81 CPM2011-161 ICD2011-93 CPSY2011-48 DC2011-57 RECONF2011-49 |
Lithography is one of the key technologies for semiconductor device shrink. For example, wave length becomes shorter an... [more] |
VLD2011-81 CPM2011-161 ICD2011-93 CPSY2011-48 DC2011-57 RECONF2011-49 p.171(VLD), p.65(CPM), p.65(ICD), p.33(CPSY), p.171(DC), p.45(RECONF) |
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