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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
ICD, CPSY |
2015-12-18 14:55 |
Kyoto |
Kyoto Institute of Technology |
Topology Optimization of 3D-Stacked Chips under Maxiumum Wire Length Constraint Hiroshi Nakahara, Daichi Fujiki, Seiichi Tade, Ryota Yasudo, Ryuta Kawano, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Koji Nakano (Hiroshima Univ.), Hideharu Amano (Keio Univ.) ICD2015-91 CPSY2015-104 |
(To be available after the conference date) [more] |
ICD2015-91 CPSY2015-104 pp.111-116 |
CPSY, DC, IPSJ-ARC (Joint) [detail] |
2015-08-05 11:45 |
Oita |
B-Con Plaza (Beppu) |
Topology Alterable NoC with fault tolerance Seiichi Tade (Keio Univ.), Michihiro Koibuchi (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.) CPSY2015-28 DC2015-24 |
(To be available after the conference date) [more] |
CPSY2015-28 DC2015-24 pp.143-148(CPSY), pp.15-20(DC) |
CPSY, DC (Joint) |
2014-07-29 11:35 |
Niigata |
Toki Messe, Niigata |
Alterable uniform and random NoC through rewiring Seiichi Tade, Ryuta Kawano, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) CPSY2014-22 |
Recently, the number of cores inside a chip has been increased. Network-on-Chip(NoC) is widely utilized for communicatio... [more] |
CPSY2014-22 pp.73-78 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-29 10:50 |
Kanagawa |
Hiyoshi Campus, Keio University |
A configurable switch mechanism for random NoCs Seiichi Tade, Takahiro Kagami, Ryuta Kawano, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) VLD2013-123 CPSY2013-94 RECONF2013-77 |
A practical method for making use of the small world phenomenon to increase Network-on-Chips (NoCs)
is proposed. Recent... [more] |
VLD2013-123 CPSY2013-94 RECONF2013-77 pp.125-130 |
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