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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 10件中 1~10件目  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
MRIS, ITE-MMS 2018-07-06
16:35
Tokyo Waseda Univ. Ultra-high-efficient Writing in Voltage-Control Spintronics Memory(VoCSM)
Altansargai Buyandalai, Mariko Shimizu, Hiroaki Yoda, Tomoaki Inokuchi, Yuichi Ohsawa, Naoharu Shimomura, Satoshi Shirotori, Hideyurki Sugiyama, Yushi Kato, Mizue Ishikawa, Katsuhiko Koi, Soichi Oikawa, Kazutaka Ikegami, Satoshi Takaya, Shinobu Fujita, Atsushi Kurobe (Toshiba Corporation)
 [more]
SDM 2017-02-06
16:10
Tokyo Tokyo Univ. [Invited Talk] Direct Cu metallization on TGV Glass substrate using Wet Process.
Kotoku Inoue, Masatoshi Takayama, Tsubasa Fujimura, Shigeo Onitake (Koto) SDM2016-146
It is believed that conformal metallization or via filling on glass with the highly conductive thick Cu material is expe... [more] SDM2016-146
pp.41-44
SDM 2016-01-28
15:20
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] MTJ based "Normally-off processors" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and Last Level Cache based on 1T-1MTJ cell and novel error handling scheme
Kazutaka Ikegami, Hiroki Noguchi, Satoshi Takaya, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Eiji Kitagawa, Takao Ochiai, Naoharu Shimomura, Daisuke Saida, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) SDM2015-126
MTJ-based cache memory is expected to reduce processor power significantly. However, write energy increases rapidly for ... [more] SDM2015-126
pp.27-30
ICD 2015-04-17
12:40
Nagano   [Invited Talk] Low-power Embedded Perpendicular STT-MRAM Design for Cache Memory
Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Chika Tanaka, Chikayoshi Kamata, Minoru Amano, Eiji Kitagawa, Naoharu Shimomura, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) ICD2015-10
 [more] ICD2015-10
pp.45-50
SDM, ICD 2013-08-01
13:45
Ishikawa Kanazawa University [Invited Talk] Design and diagnosis of 100GB/s Wide I/O with 4096b TSVs through Active Silicon Interposer
Makoto Nagata, Satoshi Takaya (Kobe Univ.), Hiroaki Ikeda (ASET) SDM2013-71 ICD2013-53
A 4096-bit wide I/O bus structure is designed and demonstrated with a three dimensional chip stack incorporating memory,... [more] SDM2013-71 ICD2013-53
pp.31-34
ICD, ITE-IST 2011-07-22
10:25
Hiroshima Hiroshima Institute of Technology Analysis Methods of Substrate Sensitivity in an Analog Circiut
Satoshi Takaya, Yoji Bando (Kobe Univ.), Toru Ohkawa, Masaaki Souda, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete), Makoto Nagata (Kobe Univ.) ICD2011-28
Substrate noise sensitivity of an analog circuit consists of the sensitivity of a device and noise propagation from the ... [more] ICD2011-28
pp.73-78
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-11-29
11:20
Fukuoka Kyushu University A Consideration of Substrate Noise Sensitivity of Analog Elements
Satoshi Takaya, Yoji Bando, Takashi Hasegawa (Kobe Univ.), Toru Ohkawa, Masaaki Souda, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete), Makoto Nagata (Kobe Univ.) CPM2010-126 ICD2010-85
Measure substrate sensitivity of differential amplifiers in a 90 nm CMOS technology with more than 32 different geometor... [more] CPM2010-126 ICD2010-85
pp.13-17
AI, SC 2010-08-23
11:50
Tokyo NII Semantic Retrieval for natural language texts by using conceptual graphs
Satoshi Takayama, Mitsuru Ishizuka (Univ. of Tokyo), Hiroshi Uchida (The UNDL Foundation) AI2010-14
 [more] AI2010-14
pp.25-29
ICD, ITE-IST 2010-07-22
10:20
Osaka Josho Gakuen Osaka Center In-situ Evaluation of Vth and AC Gain of 90 nm CMOS Differential Pair Transistors
Yoji Bando, Satoshi Takaya, Takashi Hasegawa (Kobe Univ.), Toru Ohkawa, Masaaki Souda, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete), Makoto Nagata (Kobe Univ.) ICD2010-23
 [more] ICD2010-23
pp.11-14
ICD 2009-12-14
13:30
Shizuoka Shizuoka University (Hamamatsu) [Poster Presentation] Simulation of Substrate Noise Impact on CMOS Analog Circuit
Satoshi Takaya, Yoji Bando, Makoto Nagata (Kobe Univ.) ICD2009-81
We have measured and simulated substrate noise impact on basic analog amplifier using 90-nm CMOS test chip. To measure s... [more] ICD2009-81
pp.31-34
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