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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 13 of 13  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM, ICD, ITE-IST [detail] 2018-08-09
14:35
Hokkaido Hokkaido Univ., Graduate School of IST M Bldg., M151 [Invited Talk] Cu Atom Switch Technology toward 28nm Nonvolatile Programmable Logic
Ryusuke Nebashi, Naoki Banno, Makoto Miyamura, Ayuka Morioka, Bai Xu, Koichiro Okamoto, Noriyuki Iguchi, Hideaki Numata, Hiromitsu Hada, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada (NEC) SDM2018-51 ICD2018-38
 [more] SDM2018-51 ICD2018-38
pp.131-135
ICD 2017-04-21
11:00
Tokyo   [Invited Lecture] Highly reliable Cu atom switch using thermally tolerant Polymer-solid Electrolyte (TT-PSE) for Nonvolatile Programmable Logic
Koichiro Okamoto, Munehiro Tada, Naoki Banno, Noriyuki Iguchi, Hiromitsu Hada, Toshitsugu Sakamoto, Makoto Miyamura, Yukihide Tsuji, Ryusuke Nebashi, Ayuka Morioka, Xu Bai, Tadahiko Sugibayashi (NEC) ICD2017-13
Robust Cu atom switch with higher operation reliability has been developed featuring an over-400C thermally tolerant pol... [more] ICD2017-13
pp.67-72
ICD 2017-04-21
11:25
Tokyo   [Invited Lecture] A 2x Logic Density Programmable Logic Array using Atom Switch
Yukihide Tsuji, Xu Bai, Ayuka Morioka, Miyamura Makoto, Ryusuke Nebashi, Toshitsugu Sakamoto, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada, Tadahiko Sugibayashi (NEC) ICD2017-14
(To be available after the conference date) [more] ICD2017-14
pp.73-78
ICD, SDM 2014-08-04
14:55
Hokkaido Hokkaido Univ., Multimedia Education Bldg. [Invited Talk] A 90-nm Three-terminal MRAM Embedded Nonvolatile Microcontroller for Standby-Power-Critical Applications
Noboru Sakimura, Yukihide Tsuji, Ryusuke Nebashi, Hiroaki Honjo, Ayuka Morioka, Kunihiko Ishihara (NEC), Keizo Kinoshita, Shunsuke Fukami (Tohoku Univ.), Sadahiko Miura (NEC), Naoki Kasai, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu (Tohoku Univ.), Tadahiko Sugibayashi (NEC) SDM2014-69 ICD2014-38
 [more] SDM2014-69 ICD2014-38
pp.39-44
ICD 2014-04-17
15:15
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Lecture] Fabrication of a 99%-Energy-Less Nonvolatile Multi-Functional CAM Chip Using Hierarchical Power Gating for a Massively-Parallel Full-Text-Search Engine
Shoun Matsunaga (Tohoku Univ.), Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi (NEC), Masanori Natsui, Akira Mochizuki, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu (Tohoku Univ.) ICD2014-8
We demonstrate a 1-Mb nonvolatile TCAM-based search engine using 90-nm CMOS and perpendicular MTJ technologies for an ul... [more] ICD2014-8
pp.39-44
ICD 2014-04-18
15:15
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Lecture] A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop
Hiroki Koike (Tohoku Univ.), Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Sadahiko Miura, Hiroaki Honjo, Tadahiko Sugibayashi (NEC), Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh (Tohoku Univ.) ICD2014-17
We propose a novel power-gated microprocessor unit (MPU) using a nonvolatile flip-flop (NV-F/F) with magnetic tunnel jun... [more] ICD2014-17
pp.85-90
ICD 2013-04-11
16:20
Ibaraki Advanced Industrial Science and Technology (AIST) Highly Reliable Logic Primitive Gates for Spintronics-Based Logic LSI
Yukihide Tsuji, Ryusuke Nebashi, Noboru Sakimura, Ayuka Morioka, Hiroaki Honjo, Keiichi Tokutome, Sadahiko Miura (NEC), Tetsuhiro Suzuki (Renesas Electronics Corp.), Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno (Tohoku Univ.), Tadahiko Sugibayashi (NEC) ICD2013-9
Implementing redundancy within a Spintronis Primitive Gata (SPG) using multi-terminal DWM cells ensures high reliability... [more] ICD2013-9
pp.41-46
ICD 2012-04-24
10:50
Iwate Seion-so, Tsunagi Hot Spring (Iwate) A Non-Volatile Content Addressable Memory Using Three-Terminal Magnetic Domain Wall Motion Cells
Ryusuke Nebashi, Noboru Sakimura, Yukihide Tsuji (NEC), Shunsuke Fukami (Tohoku Univ.), Hiroaki Honjo, Shinsaku Saito, Sadahiko Miura, Nobuyuki Ishiwata (NEC), Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno (Tohoku Univ.), Tadahiko Sugibayashi (NEC) ICD2012-10
A 5-ns search operation of a non-volatile content addressable memory was demonstrated. The CAM macro, with a capacity of... [more] ICD2012-10
pp.49-54
ICD, SDM 2009-07-17
14:10
Tokyo Tokyo Institute of Technology Low Current Perpendicular Domain Wall Motion Cell for Scalable High-Speed MRAM
Shunsuke Fukami, Tetsuhiro Suzuki, Kiyokazu Nagahara, Norikazu Ohshima (NEC Corp.), Yasuaki Ozaki (NECEL Corp.), Shinsaku Saito, Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Kaoru Mori, Chuji Igarashi, Sadahiko Miura, Nobuyuki Ishiwata, Tadahiko Sugibayashi (NEC Corp.) SDM2009-114 ICD2009-30
We have developed a new magnetic random access memory with current-induced domain wall motion (DW-motion MRAM) using per... [more] SDM2009-114 ICD2009-30
pp.91-95
ICD 2009-04-13
14:30
Miyagi Daikanso (Matsushima, Miyagi) [Invited Talk] MRAM technology trend and evolution, 32Mb MRAM development
Tadahiko Sugibayashi, Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Shinsaku Saito (NEC), Yuichi Ito (NECEL), Sadahiko Miura, Yuko Kato, Kaoru Mori (NEC), Yasuaki Ozaki, Yosuke Kobayashi (NECEL), Norikazu Ohshima, Keizo Kinoshita, Tetsuhiro Suzuki, Kiyokazu Nagahara (NEC) ICD2009-3
 [more] ICD2009-3
pp.13-17
ICD 2008-04-18
13:55
Tokyo   A 4-Mb MRAM macro comprising shared write-selection transistor cells and using a leakage-replication read scheme
Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, Hiroaki Honjo, Shinsaku Saito, Yuko Kato, Naoki Kasai (NEC) ICD2008-12
We propose an MRAM macro architecture for SoCs to reduce their area size. The shared write-selection transistor (SWST) a... [more] ICD2008-12
pp.63-68
ICD 2008-04-18
14:20
Tokyo   A 250-MHz 1-Mbit Embedded MRAM Macro Using 2T1MTJ Cell with Bitline Separation and Half-pitch Shift Architecture
Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Hiroaki Honjo, Shinsaku Saito, Yuko Kato, Naoki Kasai (NEC) ICD2008-13
A 250-MHz 1-Mbit MRAM macro is demonstrated in a 0.15-um standard CMOS process with 1.5V supply. Its clock frequency is ... [more] ICD2008-13
pp.69-74
ICD 2007-04-12
09:00
Oita   MRAM Cell Technology for High-speed SoCs
Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Hiroaki Honjo, Kenichi Shimura, Naoki Kasai (NEC) ICD2007-1
We has succeeded in developing new MRAM cell technology suitable for high-speed memory macro embedded in next generation... [more] ICD2007-1
pp.1-5
 Results 1 - 13 of 13  /   
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