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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, IPSJ-ARC 2012-01-20
15:10		 Tokyo   An Evaluation of An FPGA Based on Synchronous/Asynchronous Hybrid Architecture
Yoshiya Komatsu, Masanori Hariyama, Shota Ishihara, Ryoto Tsuchiya, Michitaka Kameyama (Tohoku Univ.) ICD2011-142		 This paper presents an FPGA architecture that combines synchronous and asynchronous architectures. Datapath components s... [more] ICD2011-142
pp.93-96
RECONF 2010-09-17
10:15		 Shizuoka Shizuoka University (Faculty of Eng., Hall 2) Structure of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture
Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2010-33		 Asynchronous circuit is power-efficient for low-workload sub-circuits since there is no power consumption of the clock t... [more] RECONF2010-33
pp.91-95
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