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Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY 2013-10-03
11:10		 Chiba Makuhari Messe TMR execution on SmartCore system for dependable many-core processors
Ryosuke Sasakawa, Shimpei Sato, Kenji Kise (Tokyo Inst. of Tech.) CPSY2013-32		 In order to improve the chip-level dependability, we have proposed SmartCore system, NoC-based DMR(Dual Modular Redundan... [more] CPSY2013-32
pp.7-12
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2012-11-27
09:25		 Fukuoka Centennial Hall Kyushu University School of Medicine Rethinking virtual channel usage in network-on-chip
Ryosuke Sasakawa, Naoki Fujieda, Shinya Takamaeda-Yamazaki, Kenji Kise (Tokyo Tech) CPSY2012-51		 An important requirement of routing algorithm is the freedom from deadlock in Network-on-Chip (NoC).For generating deadl... [more] CPSY2012-51
pp.21-26
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-18
16:05		 Kanagawa Keio Univ (Hiyoshi Campus) A Validation of FPGA-based Many-core Simulator ScalableCore System
Shinya Takamaeda, Ryosuke Sasakawa, Kenji Kise (Tokyo Tech) VLD2010-112 CPSY2010-67 RECONF2010-81		 We have proposed and been developing the ScalableCore system, FPGA-based simulation system for tile many-core architectu... [more] VLD2010-112 CPSY2010-67 RECONF2010-81
pp.187-192
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