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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM, VLD | 2007-10-30 13:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Electro-Thermal Compact Model for Reset Operation of Phase Change Memories Atsushi Sakai, Kenichiro Sonoda, Masahiro Moniwa, Kiyoshi Ishikawa, Osamu Tsuchiya, Yasuo Inoue (Renesas Technology Corp.)  VLD2007-55 SDM2007-199 |
A three-dimensional (3D) electro-thermal compact model for the reset operation of a phase change memory (PCM) cell is pr... [more] | VLD2007-55 SDM2007-199 pp.23-26 |
| SDM, VLD | 2007-10-30 15:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Impact of Shear Strain and Quantum Confinement on <110> Channel nMOSFET with High-Stress CESL Hiroyuki Takashino, Takeshi Okagaki, Tetsuya Uchida, Takashi Hayashi, Motoaki Tanizawa, Eiji Tsukuda, Katsumi Eikyu, Shoji Wakahara, Kiyoshi Ishikawa, Osamu Tsuchiya, Yasuo Inoue (Renesas Technology Corp.) VLD2007-57 SDM2007-201 |
Numerical study in conjunction with comprehensive bending experiments has demonstrated that \orientation{100}-Si has th... [more] |
VLD2007-57 SDM2007-201 pp.33-36 |
| SDM, VLD | 2007-10-30 15:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Validation of the Effect of Full Stress Tensor in HoleTransport in Strained 65nm-node pMOSFETs Eiji Tsukuda (Renesas), Yoshinari Kamakura (Osaka Univ.), Hiroyuki Takashino, Takeshi Okagaki, Tetsuya Uchida, Takashi Hayashi, Motoaki Tanizawa, Katsumi Eikyu, Shoji Wakahara, Kiyoshi Ishikawa, Osamu Tsuchiya, Yasuo Inoue (Renesas), Kenji Taniguchi (Osaka Univ.) VLD2007-59 SDM2007-203 |
We have developed a system consisting of a full-3D process simulator for stress calculation and k·pband calculation... [more] | VLD2007-59 SDM2007-203 pp.43-46 |
| SDM, VLD | 2006-09-26 10:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Global Identification of Variability Factors and Its Application to the Statistical Worst-Case Model Generation Katsumi Eikyu, Takeshi Okagaki, Motoaki Tanizawa, Kiyoshi Ishikawa, Osamu Tsuchiya (Renesas) |
A novel methodology is presented to generate the worst-case model including extraction of its compact model parameters. ... [more] | VLD2006-41 SDM2006-162 pp.13-18 |
| SDM, VLD | 2006-09-26 11:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Modeling of Discrete Dopant Effects on Threshold Voltage Shift by Random Telegraph Signal Ken'ichiro Sonoda, Kiyoshi Ishikawa, Takahisa Eimori, Osamu Tsuchiya (Renesas Technology Corp.) |
This paper discusses the discrete channel dopant effects on the threshold voltage shift by random telegraph signal (RTS)... [more] | VLD2006-42 SDM2006-163 pp.19-24 |
| ICD, SDM | 2006-08-18 15:25 |
Hokkaido | Hokkaido University | Impact of Random Telegraph Signals on Scaling of Multilevel Flash Memories Hideaki Kurata, Kazuo Otsuga, Akira Kotabe, Shinya Kajiyama, Taro Osabe, Yoshitaka Sasago (Hitachi), Shunichi Narumi, Kenji Tokami, Shiro Kamohara, Osamu Tsuchiya (Renesas) |
This paper describes for the first time the observation of the threshold voltage (Vth) fluctuation due to random telegra... [more] | SDM2006-153 ICD2006-107 pp.161-166 |
| ICD | 2005-04-14 16:15 |
Fukuoka | 4Gb Multilevel AG-AND Flash Memory with 10MB/s Programming Throughput Hideaki Kurata, Yoshitaka Sasago, Kazuo Otsuga, Tsuyoshi Arigane, Tetsufumi Kawamura, Takashi Kobayashi, Hitoshi Kume (Hitachi), Kazuki Homma, Kenji Kozakai, Satoshi Noda, Teruhiko Ito, Masahiro Shimizu, Yoshihiro Ikeda, Osamu Tsuchiya, Kazunori Furusawa (RENESAS) |
We fabricated a 4Gb multilevel AG-AND flash memory using 90nm CMOS technology. By using an inversion-layer local-bitline... [more] | ICD2005-11 pp.53-58 |
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