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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
SDM, ICD |
2013-08-02 15:10 |
Ishikawa |
Kanazawa University |
[Invited Talk]
A single chip LTE capable communication processor R-Mobile U2 and its technologies in power management
-- Clock control method by the power saver -- Masaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi (Renesas Mobile Corp.), Kazuki Fukuoka, Noriaki Maeda, Koji Nii (Renesas Electronics Corp.), Takeshi Kataoka, Toshihiro Hattori (Renesas Mobile Corp.) SDM2013-84 ICD2013-66 |
The “R-Mobile U2” is a single chip integration of LTE capable base band and 1.5 GHz dual-core application processor. In ... [more] |
SDM2013-84 ICD2013-66 pp.99-103 |
ICD |
2013-04-12 15:30 |
Ibaraki |
Advanced Industrial Science and Technology (AIST) |
[Invited Lecture]
Reduction of SRAM Standby Leakage utlizing All Digital Current Comparator Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki (Renesas Electronics) ICD2013-21 |
A high-performance and low-leakage current embedded SRAM for mobile phones is proposed. The proposed SRAM has two low-vo... [more] |
ICD2013-21 pp.109-114 |
ICD |
2010-04-22 11:15 |
Kanagawa |
Shonan Institute of Tech. |
A 40-nm Low-power SRAM with Multi-stage Replica-Bitline Scheme for Reducing Timing Variation Shigenobu Komatsu, Masanao Yamaoka (HITACHI), Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki (Renesas Technology Corp.), Kenichi Osada (HITACHI) ICD2010-4 |
A multi-stage replica bitline scheme for reducing access time by suppressing enable timing variation of a sense amplifie... [more] |
ICD2010-4 pp.17-21 |
ICD |
2008-04-17 10:15 |
Tokyo |
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[Invited Talk]
65nm Low-Power High-Density SRAM Operable at 1.0V under 3sigma Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS Masanao Yamaoka (Hitachi, Ltd.), Noriaki Maeda, Yasuhisa Shimazaki (Renesas), Kenichi Osada (Hitachi, Ltd.) ICD2008-2 |
A 1Mb SRAM is fabricated in 65nm LP process with 0.51μm2 cell. An NMOS and PMOS separately applied body bias technique a... [more] |
ICD2008-2 pp.7-12 |
ICD |
2005-04-14 09:30 |
Fukuoka |
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Low-Power Embedded SRAM Modules with Expanded Margins for Writing Masanao Yamaoka (Hitachi, Ltd.), Noriaki Maeda (Renesas), Yoshihiro Shinozaki (Hitachi ULSI), Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa (Renesas), Takayuki Kawahara (Hitachi, Ltd.) |
The power consumption of a low-power SoC has a battery life of mobile appliances. The general SoCs have large on-chip SR... [more] |
ICD2005-2 pp.7-12 |
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