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Abstract
Paper #
CPSY
,
VLD
,
IPSJ-SLDM
2005-01-25
10:00
Kanagawa
Reconfigurable 1-bit processor array with reduced wiring area
Nobuo Nakai
,
Masaki Nakanishi
,
Shigeru Yamashita
,
Katsumasa Watanabe
(
NAIST
)
Semiconductor makers have a problem of how to reduce the production cost. Because of the increasing gates to implement a...
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VLD2004-98
CPSY2004-64
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