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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 14 of 14  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, DC
(Joint)		 2014-07-28
17:25		 Niigata Toki Messe, Niigata Fast Evaluation Method based on Static Code Analysis for Programs Derived by the Iterative Optimization on the Polyhedral Model
Tomoyuki Hosaka, Nobuhiko Sugino (Tokyo Inst. of Tech.) CPSY2014-14		 For evaluation scheme in source code transformation, a fast evaluation method based on static code analysis is proposed.... [more] CPSY2014-14
pp.25-30
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] 2012-03-02
15:15		 Miyagi   Profiling-based Source to Source Compiler for GPGPU
Atsushi Yumoto, Nobuhiko Sugino (Titech) CPSY2011-83 DC2011-87		 A new profiling-based C to CUDA compiler for GPCPU is proposed in order to help developing higher performance GPGPU appl... [more] CPSY2011-83 DC2011-87
pp.79-84
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] 2012-03-03
11:00		 Miyagi   An Automatic Parallelization Scheme Used in JIT Compilation for Dynamic Language Applications
Ryotaro Ikeda, Nobuhiko Sugino (Tokyo Tech) CPSY2011-90 DC2011-94		 An automatic parallelization scheme for dynamic language applications under interpreter ex-ecution environment is propos... [more] CPSY2011-90 DC2011-94
pp.187-192
SIP, CAS, CS 2010-03-02
09:20		 Okinawa Hotel Breeze Bay Marina, Miyakojima Preprocessing Method based on Operation Instruction Clustering of Code Optimization for a Processor Architecture with Bypass Chain
Yuki Kamada, Toshihiro Shoji, Jin Tian, Nobuhiko Sugino (Tokyou Inst. of Tech.) CAS2009-108 SIP2009-153 CS2009-103		 For a processor with a bypass chain, a novel code optimization method based on data flow graph (DFG) form is discussed. ... [more] CAS2009-108 SIP2009-153 CS2009-103
pp.173-178
SIP, CAS, CS 2010-03-02
13:45		 Okinawa Hotel Breeze Bay Marina, Miyakojima [Poster Presentation] Automatic Code Parallelization base on quantitative evaluation of data transfer for multi-layered cache architecture
Takuya Noritake, Nobuhiko Sugino (Tokyo Inst. of Tech.) CAS2009-119 SIP2009-164 CS2009-114		 An automatic code parallelization method based on quantitative evaluation of data transfer for multi-layered cache archi... [more] CAS2009-119 SIP2009-164 CS2009-114
pp.235-236
SIP, CAS, CS 2010-03-02
13:45		 Okinawa Hotel Breeze Bay Marina, Miyakojima [Poster Presentation] Low Power Processor Architecture based on a Dynamic Reconfigurable Scheme in Pipeline Stages
Masashi Ohki, Nobuhiko Sugino (Tokyo Inst. of Tech.) CAS2009-120 SIP2009-165 CS2009-115		 A processor architecture which can execute instructions in dynamic reconfigurable pipeline manner is proposed. By help o... [more] CAS2009-120 SIP2009-165 CS2009-115
pp.237-238
CS, SIP, CAS 2008-03-07
13:00		 Yamaguchi Yamaguchi University [Poster Presentation] Code Optimization Method for Bypass Network Architechture by Evalation of DFG
Toshihiro Shoji, Jin Tian, Takefumi Miyoshi, Nobuhiko Sugino (Tokyo Tech．) CAS2007-139 SIP2007-214 CS2007-104		 For a bypass interconnected processor architecture, a heuristic code optimization method is proposed. In total power c... [more] CAS2007-139 SIP2007-214 CS2007-104
pp.75-78
CAS, SIP, CS 2006-03-06
14:20		 Okinawa Univ of Ryukyu A VLIW compiler to combine multiple code optimization methods
Yuhei Kaneko, Nobuhiko Sugino (Tokyo Institute of Tech.) 		 [more] CAS2005-114 SIP2005-160 CS2005-107
pp.105-109
CAS, SIP, VLD 2005-06-28
13:00		 Miyagi Tohoku University A compiler framework to combine multiple code optimization methods
Yuhei Kaneko, Nobuhiko Sugino (Tokyo Institute of Tech.) 		 [more] CAS2005-19 VLD2005-30 SIP2005-43
pp.25-29
CAS 2005-01-21
14:15		 Ishikawa Kanazawa Univ A technique to analyze bus architecture driven by data stream
Takefumi Miyoshi, Nobuhiko Sugino (Tokyo Inst. of Tech.) 		 [more] CAS2004-75
pp.19-22
CAS 2005-01-21
14:40		 Ishikawa Kanazawa Univ
Yuhei Kaneko, Nobuhiko Sugino, Akinori Nishihara (Tokyo Inst. of Tech.) 		 [more] CAS2004-76
pp.23-27
CAS 2005-01-21
15:05		 Ishikawa Kanazawa Univ On the implementation of digital lock-in-amp
Nobuhiro Miyaoka, Akiyoshi Yonekura, Nobuhiko Sugino (Tokyo Inst. of Tech.) 		 [more] CAS2004-77
pp.29-34
MSS, CAS 2004-11-05
09:55		 Aichi Aichi Pref. Univ. Memory allocation method for indirect addressing DSP with discrete auto-modification
Nobuhiko Sugino, Yuhei Kaneko, Akinori Nishihara (Tokyo Inst. of Tech.) 		 [more] CAS2004-57 CST2004-36
pp.7-12
NLP, CAS 2004-09-14
15:45		 Kyoto Kyoto Univ. Computational Ordering Method with Consideration of Memory Access by Auto-Modification Indirect Addressing
Yuhei Kaneko, Nobuhiko Sugino, Akinori Nishihara (Tokyo Inst. of Tech.) 		 [more] CAS2004-41 NLP2004-53
pp.79-84
 Results 1 - 14 of 14  /   
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