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Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
16:00
Kanagawa   Break Even Time Evaluation of Run-Time Power Gating Control by On-chip Leakage Monitor
Kensaku Matsunaga, Masaru Kudo (SIT), Yuya Ohta, Nao Konishi (SIT), Hideharu Amano (KU), Ryuichi Sakamoto, Mitaro Namiki (TUAT), Kimiyoshi Usami (SIT) VLD2012-118 CPSY2012-67 RECONF2012-72
Run-time Power Gating (RTPG) reduces leakage energy by turning off a power switch(PS) for idle periods of a circuit duri... [more] VLD2012-118 CPSY2012-67 RECONF2012-72
pp.63-68
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
13:25
Fukuoka Centennial Hall Kyushu University School of Medicine Analytical model of energy dissipation for comparing adder architectures
Nao Konishi, Kimiyoshi Usami (Shibaura I.T.) VLD2012-80 DC2012-46
This paper describes analytical models for delay and energy dissipation of ripple-carry, carry look-ahead, and parallel ... [more] VLD2012-80 DC2012-46
pp.123-128
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-12-01
14:50
Fukuoka Kyushu University Optimal adder architecture in ultra low voltage domain
Nao Konishi, Masaru Kudo, Kimiyoshi Usami (Shibaura Inst. Tech.) VLD2010-81 DC2010-48
Circuit performance is evaluated for several adder architectures with wiring capacitance extracted from layout at 65nm p... [more] VLD2010-81 DC2010-48
pp.173-178
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