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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 48  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS, VLD [detail] 2020-03-05
10:30
Okinawa Okinawa Ken Seinen Kaikan Motor Current Signature Analysis Based On-Line Fault Detection of DC Motor
Naoki Osako (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM), Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2019-111 HWS2019-84
This article presents a method for online detection of DC motors' fault based on current signature analysis.
While cu... [more]
VLD2019-111 HWS2019-84
pp.101-106
HWS, VLD [detail] 2020-03-05
13:00
Okinawa Okinawa Ken Seinen Kaikan Hardware Control from Erlang Programs on Programmable SoC
Hidekazu Wakabayashi (Kwansei Gakuin Univ.), Nagisa Ishiura (Kwnsei Gakuin Univ.) VLD2019-114 HWS2019-87
This article presents a method for controlling custom hardware from Erlang programs.
Higher and higher functionality, ... [more]
VLD2019-114 HWS2019-87
pp.119-124
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-22
15:25
Kanagawa Raiosha, Hiyoshi Campus, Keio University Increasing Test Variation for C Compilers by Equivalent Mutant Generation
Hiroki Maeda, Nagisa ishiura (Kwansei Gakuin Univ.) VLD2019-61 CPSY2019-59 RECONF2019-51
This article proposes a method of increasing variation of test programs in automatic testing of C compilers by means of ... [more] VLD2019-61 CPSY2019-59 RECONF2019-51
pp.43-48
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-22
15:50
Kanagawa Raiosha, Hiyoshi Campus, Keio University Mutation Fuzzing Based on Type Estimation of Data Items Utilizing Data Writer
Yoko Higuchi, Nagisa Ishiura, Namba Noriyuki (Kwansei Gakuin Univ.) VLD2019-62 CPSY2019-60 RECONF2019-52
This article proposes a novel way of acquiring information, which is used for enhancing efficiency of fuzzing for softwa... [more] VLD2019-62 CPSY2019-60 RECONF2019-52
pp.49-53
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-23
11:25
Kanagawa Raiosha, Hiyoshi Campus, Keio University Full Hardware Synthesis of FreeRTOS-Based Systems
Wakako Nakano, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2019-70 CPSY2019-68 RECONF2019-60
 [more] VLD2019-70 CPSY2019-68 RECONF2019-60
pp.105-110
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-23
11:50
Kanagawa Raiosha, Hiyoshi Campus, Keio University Binary Synthesis from RISC-V Executables
Shoki Hamana, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2019-71 CPSY2019-69 RECONF2019-61
This article presents a method of synthesizing hardware from RISC-V binary codes. RISC-V is an open source instruction s... [more] VLD2019-71 CPSY2019-69 RECONF2019-61
pp.111-115
HWS, VLD 2019-03-01
10:00
Okinawa Okinawa Ken Seinen Kaikan Synthesis of Full Hardware Implementation of RTOS-Based Systems
Yuuki Oosako, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2018-122 HWS2018-85
This paper presents a method of automatically synthesizing a hardware
design from a set of source codes for a real-time... [more]
VLD2018-122 HWS2018-85
pp.175-180
HWS, VLD 2019-03-01
10:50
Okinawa Okinawa Ken Seinen Kaikan Reinforcing Generation of Instruction Sequences in Random Testing of Android Virtual Machine
Ryotaro Shimizu, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2018-124 HWS2018-87
This article presents a method of reinforcing generation of instruction sequences in random testing of the Android virtu... [more] VLD2018-124 HWS2018-87
pp.187-192
HWS, VLD 2019-03-01
11:15
Okinawa Okinawa Ken Seinen Kaikan Synthesis of Distributed Control Circuits for Dynamic Scheduling across Multiple Dataflow Graphs
Sayuri Ota, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2018-125 HWS2018-88
This article presents a method for synthesizing circuits with distributed control from CDFGs (control data flow graphs).... [more] VLD2018-125 HWS2018-88
pp.193-198
VLD, HWS
(Joint)
2018-02-28
13:30
Okinawa Okinawa Seinen Kaikan Random Testing of Android Virtual Machine by Valid Dex File Generation
Hirofumi Ikeo, Ryotaro Shimizu, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2017-95
 [more] VLD2017-95
pp.37-42
IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2018-01-18
17:00
Kanagawa Raiosha, Hiyoshi Campus, Keio University Distributed Memory Architecture for High-Level Synthesis from Erlang
Kagumi Azuma, Shoki Hamana, Hidekazu Wakabayashi, Nagisa Ishiura (Kwansei Gakuin Univ.), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM) VLD2017-75 CPSY2017-119 RECONF2017-63
This paper presents a distributed memory architecture for dedicated
hardware automatically synthesized from Erlang prog... [more]
VLD2017-75 CPSY2017-119 RECONF2017-63
pp.77-82
IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2018-01-19
16:15
Kanagawa Raiosha, Hiyoshi Campus, Keio University Reinforcing Generation of Control Flow Statements in Random Test System of C Compilers Based on Equivalence Transformation
Mitsuyoshi Iwatsuji, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2017-87 CPSY2017-131 RECONF2017-75
This article proposes a method of reinforcing generation of control statements in random testing of compilers based on e... [more] VLD2017-87 CPSY2017-131 RECONF2017-75
pp.163-168
IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2018-01-19
16:40
Kanagawa Raiosha, Hiyoshi Campus, Keio University Mutant Generation of Performance Tests for LLVM Back-Ends
Kenji Tanaka, Nagisa Ishiura (Kwansei Gakuin Univ.), Masanari Nishimura, Akiya Fukui (Renesas) VLD2017-88 CPSY2017-132 RECONF2017-76
This article presents a method of testing optimization capability of LLVM back-ends by generating functionally equivalen... [more] VLD2017-88 CPSY2017-132 RECONF2017-76
pp.169-174
VLD 2016-02-29
13:55
Okinawa Okinawa Seinen Kaikan Random Testing of C Compilers Based on Test Program Generation by Equivalence Transformation
Kazuhiro Nakamura, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2015-112
This article proposes a method of generating test programs for random testing of C compilers based on equivalence transf... [more] VLD2015-112
pp.7-12
VLD 2016-02-29
15:00
Okinawa Okinawa Seinen Kaikan High-Level Synthesis of Embedded Systems Controller from Erlang
Hinata Takabeyashi, Nagisa Ishiura, Kagumi Azuma (Kwansei Gakuin Univ), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM) VLD2015-114
This article presents a method of specifying the behavior of embedded systems' control by a subset of Erlang and synthes... [more] VLD2015-114
pp.19-24
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-21
13:00
Kanagawa Hiyoshi Campus, Keio University Mainframe Assembly to C translation in Legacy Migration
Daisuke Fujiwara, Nagisa Ishiura, Ryo Sakai (Kwansei Gakuin Univ.), Ryo Aoki, Takashi Ogawara (SYSTEM'S) VLD2015-104 CPSY2015-136 RECONF2015-86
This article presents a method of translating mainframe assembly programs to C programs. In ``legacy migration,'' where ... [more] VLD2015-104 CPSY2015-136 RECONF2015-86
pp.203-208
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-21
13:50
Kanagawa Hiyoshi Campus, Keio University Binary Synthesis Implementing External Interrupt Handler as Independent Module
Naoya Ito, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2015-106 CPSY2015-138 RECONF2015-88
 [more] VLD2015-106 CPSY2015-138 RECONF2015-88
pp.215-220
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-03
09:45
Nagasaki Nagasaki Kinro Fukushi Kaikan Extending Distributed Control for High-Level Synthesis beyond Boundaries of Dataflow Graphs
Miho Shimizu, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2015-61 DC2015-57
This paper proposes an extension of distributed control, which enables efficient run-time scheduling of variable latency... [more] VLD2015-61 DC2015-57
pp.153-158
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-03
14:10
Nagasaki Nagasaki Kinro Fukushi Kaikan Exploration of Address Offsets of Basic Blocks for Cache Hit Ratio Improvement
Junya Goto, Nagisa Ishiura (K.G.) VLD2015-74 DC2015-70
This article proposes a method of reducing cache misses on an instruction memory by inserting offsets before basic block... [more] VLD2015-74 DC2015-70
pp.237-241
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-29
18:00
Kanagawa Hiyoshi Campus, Keio University CF3: Test suite for arithmetic optimization of C compilers
Yusuke Hibino, Nagisa Ishiura (KGU) VLD2014-130 CPSY2014-139 RECONF2014-63
This article presents a compiler test suite "CF3," which targets arithmetic optimization, especially constant folding, o... [more] VLD2014-130 CPSY2014-139 RECONF2014-63
pp.117-122
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