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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 24件中 1~20件目  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2013-12-13
13:25
Ishikawa   Variable Test-Timing Generation for Built-In Self-Test on FPGA
Yasuo Sato, Munehiro Matsuura, Hitoshi Arakawa, Yousuke Miyake, Seiji Kajihara (Kyushu Inst. of Tech.) DC2013-69
This paper proposes a variable test-timing generation method that should be used for built-in self-test on FPGA. Applica... [more] DC2013-69
pp.7-12
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-27
13:25
Kagoshima   An Update Method for a CAM Emulator using a LUT Cascade Based on an EVBDD
Kensuke Kushiyama, Hiroki Nakahara (Kagoshima Univ.), Tsutomu Sasao (Meiji Univ.), Munehiro Matsuura (Kyushu Inst. of Tech.) RECONF2013-40
The core routers forward packets by IP-lookup using longest prefix matching~(LPM) by using a content addressable memory~... [more] RECONF2013-40
pp.7-12
RECONF 2013-09-19
13:50
Ishikawa Japan Advanced Institute of Science and Technology A Packet Classifier using Parallel EVMDD(k) Machine
Hiroki Nakahara (Kagoshima Univ.), Tsutomu Sasao (Meiji Univ.), Munehiro Matsuura (Kyushu Inst. of Tech.) RECONF2013-34
A decision diagram machine~(DDM) is a special-purpose processor that
uses special instructions to evaluate a decision... [more]
RECONF2013-34
pp.85-90
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
11:00
Kanagawa   An Architecture for IPv6 Lookup Using Parallel Index Generation Units
Hiroki Nakahara (Kaoghima Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT) VLD2012-111 CPSY2012-60 RECONF2012-65
This paper shows an area-efficiency and high-performance
architecture for the IPv6 lookup using parallel index generat... [more]
VLD2012-111 CPSY2012-60 RECONF2012-65
pp.25-30
RECONF 2012-09-19
14:40
Shiga Epock Ritsumei 21, Ritsumeikan Univ. A Virus Scanning Engine Using an MPU and an IGU Based on ROW Shift Decomposition
Hiroki Nakahara (Kaoghima Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT) RECONF2012-44
This paper shows a virus scanning engine using two-stage matching.
In the first stage, a binary CAM emulator quickly de... [more]
RECONF2012-44
pp.119-124
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-25
13:30
Kanagawa Hiyoshi Campus, Keio University On a Decomposed MTMDDs for CF Machine
Hiroki Nakahara (Kagoshima Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT) VLD2011-96 CPSY2011-59 RECONF2011-55
A decomposed multi-terminal multi-valued decision diagrams for characteristic function~(MTMDDs for CF)
represents deco... [more]
VLD2011-96 CPSY2011-59 RECONF2011-55
pp.31-36
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2011-11-28
15:40
Miyazaki NewWelCity Miyazaki On a Power-Delay Product for a Heterogeneous MDD for ECFN Machine
Hiroki Nakahara (Kagoshima Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT) RECONF2011-41
This paper analyzes a power-delay product for a HMDD for an ECFN~(Heterogeneous Multi-valued Decision Diagram for Encode... [more] RECONF2011-41
pp.1-6
RECONF 2011-05-12
15:50
Hokkaido Hokkaido Univ. (Faculty of Eng., B3 Bldg.) A Virus Scanning Engine Using a 4IGU Emulator and an MPU
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (KIT) RECONF2011-10
This paper shows a virus scanning system using two-stage matching.
In the first stage, a hardware filter quickly detect... [more]
RECONF2011-10
pp.55-60
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-18
09:00
Kanagawa Keio Univ (Hiyoshi Campus) A Regular Expression Matching Circuit Based on Decomposed Automaton
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (KIT) VLD2010-98 CPSY2010-53 RECONF2010-67
In this paper, we propose a regular expression matching circuit based on
a decomposed automaton.
To implement regular... [more]
VLD2010-98 CPSY2010-53 RECONF2010-67
pp.105-110
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-11-30
13:55
Fukuoka Kyushu University On a Prefetching Heterogeneous MDD Machine
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (KIT) RECONF2010-41
This paper shows a heterogeneous multi-valued decision diagram machine~(HMDDM).
First, we introduce a standard heteroge... [more]
RECONF2010-41
pp.13-18
RECONF 2010-09-16
13:00
Shizuoka Shizuoka University (Faculty of Eng., Hall 2) A Regular Expression Matching Circuit Based on an NFA with Multi-Character Consuming
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (KIT) RECONF2010-20
This paper shows an implementation of a regular expression circuit based on an NFA~(Non-deterministic finite automaton).... [more] RECONF2010-20
pp.13-18
VLD 2010-03-12
11:15
Okinawa   A Comparison of Two Approximate String Matching Algorithms Implemented on an FPGA
Keisuke Shimizu, Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.) VLD2009-123
An approximate string matching finds the most similar pattern in the text.
A dynamic programming is used for the approx... [more]
VLD2009-123
pp.145-150
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-27
13:30
Kanagawa Keio Univ (Hiyoshi Campus) A Packet Classifier Using a Parallel Branching Program Machine
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Tech Corp.) VLD2009-92 CPSY2009-74 RECONF2009-77
A branching program machine~(BM) is a special-purpose processor that
uses only two kinds of instructions: Branch and ... [more]
VLD2009-92 CPSY2009-74 RECONF2009-77
pp.143-148
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-03
15:20
Kochi Kochi City Culture-Plaza A Virus Scanning Engine Using a Parallel Sieve Method and the MPU
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Technology Corp.) RECONF2009-45
In this paper, we show a new architecture for the virus scanning machine,
which is different from that of the intrusi... [more]
RECONF2009-45
pp.25-30
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-04
15:00
Kochi Kochi City Culture-Plaza An Optimal Algorithm for 3-adress QDD Machine Code
Taisuke Fukuyama, Tsutomu Sasao, Munehiro Matsuura (Kyusyu Inst. of Tech.) RECONF2009-52
To speed up the evaluation of logic functions, we use quaternary decision diagrams (QDDs). A 3-adress QDD machine is a b... [more] RECONF2009-52
pp.67-72
VLD 2009-03-11
15:15
Okinawa   On the Minimization of Input Variables for Incompletely Specified Index Generation Functions
Takaaki Nakamura, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.) VLD2008-133
This paper shows a method to reduce the numbers of input variables to represent incompletely specified index generation ... [more] VLD2008-133
pp.41-46
VLD 2009-03-12
13:00
Okinawa   Emulation of Sequential Circuits by a Parallel Branching Program Machine
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Technology Corp.) VLD2008-145
The parallel branching program machine~(PBM128) consists of 128 branching program machines~(BMs)
and a programmable in... [more]
VLD2008-145
pp.111-116
RECONF, CPSY, VLD, IPSJ-SLDM 2008-01-16
17:50
Kanagawa Hiyoshi Campus, Keio University A Method of Design and Update for an Address Generator Using a Hybrid Method
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (K.I.T.) VLD2007-117 CPSY2007-60 RECONF2007-63
 [more] VLD2007-117 CPSY2007-60 RECONF2007-63
pp.73-78
ICD, VLD 2007-03-08
15:10
Okinawa Mielparque Okinawa A CAM Emulator Using Look-Up Table Cascades
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.)
An address table relates k different registered vectors to the addresses from 1 to k.
An address generation function re... [more]
VLD2006-134 ICD2006-225
pp.91-96
ICD, VLD 2007-03-08
15:30
Okinawa Mielparque Okinawa Design Method of Radix Converters Using Arithmetic Decompositions (3)
Yukihiro Iguchi (Meiji Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT), Toshikazu Aoyama (Meiji Univ.)
In digital signal processing, radixes other than two are often used
for high-speed computation.
In the computation f... [more]
VLD2006-135 ICD2006-226
pp.97-102
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