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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, CPSY, RECONF, IPSJ-SLDM |
2009-01-29 15:10 |
Kanagawa |
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Improvement of Execution Efficiency by Applying Unitable PE Architecture for MX Core Yuta Mizokami, Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) VLD2008-103 CPSY2008-65 RECONF2008-67 |
MX-Core is a massively parallel SIMD(Single Instruction Multiple Data) type processor which have ne-grained computing u... [more] |
VLD2008-103 CPSY2008-65 RECONF2008-67 pp.69-74 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 13:25 |
Fukuoka |
Kitakyushu Science and Research Park |
An optimization method for MIMD controlled data communication of MX Core Akihiro Kodama, Yuta Mizokami, Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2008-42 |
The massively parallel SIMD (Single Instruction Multiple Data) processor MX Core, which has been developed by Renesas te... [more] |
CPSY2008-42 pp.31-36 |
RECONF |
2008-05-22 15:15 |
Fukushima |
The University of Aizu |
Path Planning Method for MIMD Controlled data communication in MX Core Akihiro Kodama, Yuta Mizokami, Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (kumamoto Univ.) RECONF2008-6 |
The MX core is a massively parallel SIMD (Single Instruction Multiple Data) processor based on fine-grained 1,024 PEs (P... [more] |
RECONF2008-6 pp.31-36 |
RECONF, CPSY, VLD, IPSJ-SLDM |
2008-01-17 10:15 |
Kanagawa |
Hiyoshi Campus, Keio University |
Improvement in data communication between PEs for SIMD type processor MX core Yuta Mizokami, Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ) VLD2007-121 CPSY2007-64 RECONF2007-67 |
We are researching about MX Core developed in Renesas Technology Corp.. MX Core is SIMD(Single Instruction Multiple Data... [more] |
VLD2007-121 CPSY2007-64 RECONF2007-67 pp.19-24 |
CPSY |
2007-10-25 14:20 |
Kumamoto |
Kumamoto University |
An Implementation and evaluation of Ant Colony Optimization for massively parallel SIMD processor MX Core Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ) CPSY2007-26 |
We focus on massively parallel processor based on the matrix architecture (MX Core) developed by
Renesas Technology Cor... [more] |
CPSY2007-26 pp.13-18 |
RECONF |
2006-09-15 09:00 |
Kumamoto |
Kumamoto Univ. |
An Implementation of Ant Colony Optimization for the MaTriX Processing Engine Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) |
[more] |
RECONF2006-27 pp.1-6 |
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