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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2014-03-05
11:15		 Okinawa Okinawa Seinen Kaikan Inductive-Coupling Interface for Multiple-Memory Chip Stacking
Mitsuko Saito, Tadahiro Kuroda (Keio Univ.) VLD2013-159		 Inductive-coupling interface for multiple-memory chip stacking is proposed. The number of stacked memory chips was limit... [more] VLD2013-159
pp.137-140
ICD 2013-04-11
10:50		 Ibaraki Advanced Industrial Science and Technology (AIST) [Invited Talk] An Inductive-Coupling Wake-Up Transceiver for Standby Power Reduction of Non-Contact Memory Card
Noriyuki Miura (Kobe Univ.), Mitsuko Saito, Masao Taguchi, Tadahiro Kuroda (Keio Univ.) ICD2013-3		 A normally-off-type inductive-coupling wake-up transceiver is developed to 1/500 the standby power consumption of non-co... [more] ICD2013-3
pp.11-14
ICD 2010-04-23
15:15		 Kanagawa Shonan Institute of Tech. An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR Inductive-Coupling Interface Between 65nm CMOS GPU and 0.1um DRAM
Noriyuki Miura, Kazutaka Kasuga, Mitsuko Saito, Tadahiro Kuroda (Keio Univ.) ICD2010-18		 An 8Tb/s 1pJ/b 0.8mm2/Tb/s inductive-coupling interface between 65nm CMOS GPU and 0.1um DRAM is developed. BER<10-16 ope... [more] ICD2010-18
pp.93-97
ICD 2010-04-23
15:40		 Kanagawa Shonan Institute of Tech. A 2Gb/s 1.8pJ/b/chip Inductive-Coupling Through-Chip Bus for 128-Die NAND-Flash Memory Stacking
Mitsuko Saito, Noriyuki Miura, Tadahiro Kuroda (Keio Univ.) ICD2010-19		 128 chips are stacked using a spiral stair stacking scheme. The controller accesses a random memory chip at 2Gb/s by ind... [more] ICD2010-19
pp.99-102
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