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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 5件中 1~5件目  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM, ICD, ITE-IST [detail] 2018-08-09
12:45
Hokkaido Hokkaido Univ., Graduate School of IST M Bldg., M151 Study of Impact of BTI's Local Layout Effect Including Recovery Effect on Various Standard-Cells in 10nm FinFET
Mitsuhiko Igarashi, Yuuki Uchida, Yoshio Takazawa, Yasumasa Tsukamoto, Koji Shibutani, Koji Nii (Renesas)
 [more] SDM2018-47 ICD2018-34
pp.109-113
ICD, SDM 2014-08-04
10:50
Hokkaido Hokkaido Univ., Multimedia Education Bldg. A 28nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor with 2GHz Cores and Low-Power 1GHz Cores
Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Hiroshi Kishibe, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori (Renesas Electronics)
This paper presents power management and low power techniques of our heterogeneous quad/octa-core mobile application pro... [more] SDM2014-64 ICD2014-33
pp.11-16
SDM, ICD 2013-08-02
10:50
Ishikawa Kanazawa University A 123uW Standby Power Technique with EM-Tolerant 1.8V I/O NMOS Power Switch in 28nm HKMG Technology
Kazuki Fukuoka, Ryo Mori, Akira Kato, Mitsuhiko Igarashi, Koji Shibutani, Takashi Yamaki, Koji Nii, Sadayuki Morita, Takao Koike (Renesas Electronics), Noriaki Sakamoto (Renesas Mobile)
 [more] SDM2013-78 ICD2013-60
pp.65-69
ICD 2012-12-18
10:20
Tokyo Tokyo Tech Front 28-nm HKMG GHz Digital Sensor for Detecting Dynamic Voltage Drops in Testing for Peak Power Optimization
Mitsuhiko Igarashi, Yoshio Takazawa, Yasuto Igarashi, Hiroaki Matsushita, Kan Takeuchi (Renesas Electronics)
We propose a dynamic voltage-drop sensor, which is fully digital so that it is easy to design into products and use for ... [more] ICD2012-115
pp.97-102
ED, MW 2006-01-18
15:45
Tokyo Kikai-Shinko-Kaikan Bldg. Prediction of High-Frequency Characteristics for Hot-Electron Transistors Controlled by Gate Bias
Nobuya Machida, Mitsuhiko Igarashi, Tomohiro Yamada, Yasuyuki Miyamoto, Kazuhito Furuya (Tokyo Tech.)
We performed full-band Monte Carlo simulations for the hot-electron transistor with the transit region made of the intri... [more] ED2005-197 MW2005-151
pp.29-32
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