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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, IPSJ-SLDM 2013-05-16
09:25		 Fukuoka Kitakyushu International Conference Center A Floorplan Method by Simulated Annealing and Sequence-pair for Asynchronous Circuits with Bundled-data Implementation
Minoru Iizuka, Hiroshi Saito (Univ. of Aizu) VLD2013-2		  [more] VLD2013-2
pp.7-12
IPSJ-SLDM, VLD 2012-05-31
10:55		 Fukuoka Kitakyushu International Conference Center Development of an FPGA Design Support Tool Set for Asynchronous Circuits with Bundled-data Implementation
Keitaro Takizawa, Minoru Iizuka, Hiroshi Saito (Univ. of Aizu) VLD2012-9		 This paper proposes a design support tool set for asynchronous circuits with bundled-data implemen-tation which are impl... [more] VLD2012-9
pp.49-54
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