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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, IPSJ-SLDM 2016-05-11
16:00
Fukuoka Kitakyushu International Conference Center [Invited Talk] Challenges of DA Technologies for the Future -- For the Establishment of Next Generation DA Technologies --
Michiaki Muraoka (Kochi Univ.) VLD2016-6
For the Establishment of Next Generation DA Technologies [more] VLD2016-6
p.53
RECONF 2013-05-21
09:00
Kochi Kochi Prefectural Culture Hall [Invited Talk] A Challenge of Acceleration of DA Algorithm by Parallel Processing
Michiaki Muraoka (Kochi Univ.) RECONF2013-9
 [more] RECONF2013-9
p.47
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-26
09:50
Kanagawa Keio Univ (Hiyoshi Campus) Evaluation of Hardware/Software Partitioning Method with Consideration of Software Parallelization
Junya Matsunaga, Michiaki Muraoka (Kochi Univ.), Dai Araki (InterDesign Technologies, Inc.) VLD2009-71 CPSY2009-53 RECONF2009-56
In this research , we proposed an effective hardware/software partitioning methodology based on C description with consi... [more] VLD2009-71 CPSY2009-53 RECONF2009-56
pp.13-18
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-27
14:55
Kanagawa Keio Univ (Hiyoshi Campus) An Estimation Method of Delay Time Variation by Crosstalk in Logic Circuit Level
Masayuki Kobayashi, Wataru Sento, Masahiko Toyonaga, Michiaki Muraoka (Kochi Univ.) VLD2009-95 CPSY2009-77 RECONF2009-80
In this paper, a method which detects crosstalk points and timing error points by using the logic simulation with the ba... [more] VLD2009-95 CPSY2009-77 RECONF2009-80
pp.161-166
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-02
15:20
Kochi Kochi City Culture-Plaza Evaluation of Hardware/Software Partitioning Method with Consideration of Timing
Junya Matsunaga, Michiaki Muraoka (Kochi Univ.) VLD2009-46 DC2009-33
The optimal hardware/software partitioning is an important issue in the system level design. In the conventional design,... [more] VLD2009-46 DC2009-33
pp.31-36
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-04
10:00
Kochi Kochi City Culture-Plaza A Logic Simulation Method with Consideration of Delay Time Variation by Crosstalk
Masayuki Kobayashi, Wataru Sento, Masahiko Toyonaga, Michiaki Muraoka (Kochi Univ.) VLD2009-58 DC2009-45
In this paper, a method which detects timing error points by using the logic simulation with back annotation of delay ti... [more] VLD2009-58 DC2009-45
pp.119-124
 Results 1 - 6 of 6  /   
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