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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 106  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2022-03-10
10:10
Online Online *
Hiroki Kawaguchi, Itsuki Fujita, Yoshikazu Nagamura (Tokyo Metropolitan Univ.), Masayuki Arai (Nihon Univ.), Satoshi Fukumoto (Tokyo Metropolitan Univ.) CPSY2021-55 DC2021-89
(To be available after the conference date) [more] CPSY2021-55 DC2021-89
pp.61-66
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2022-03-10
10:30
Online Online A Don't Care Filling Method of Control Signals for Concurrent Logical Fault Testing
Haofeng Xu, Toshinori Hosokawa, Hiroshi Yamazaki, Masayuki Arai (Nihon Univ), Masayoshi Yoshimura (KSU) CPSY2021-56 DC2021-90
In recent years, with the increase in test cost for VLSIs, it has been important to reduce the number of test patterns. ... [more] CPSY2021-56 DC2021-90
pp.67-72
DC 2022-03-01
16:10
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
An Estimation Method of Defect Types for Multi-cycle Capture Testing Using Artificial Neural Networks and Fault Detection Information
Natsuki Ota, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.), Masayuki Arai, Yukari Yamauchi (Nihon Univ.) DC2021-77
 [more] DC2021-77
pp.75-80
DC 2022-03-01
16:35
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
DC2021-78  [more] DC2021-78
pp.81-86
DC 2021-12-10
13:00
Kagawa
(Primary: On-site, Secondary: Online)
A Low Power Oriented Multiple Target Test Generation Method
Rei Miura, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.), Masayuki Arai (Nihon Univ.) DC2021-55
In recent years, since capture power consumption for VLSIs significantly increases in at-speed scan testing, low capture... [more] DC2021-55
pp.1-6
DC 2021-12-10
13:40
Kagawa
(Primary: On-site, Secondary: Online)
 [more]
DC, CPSY, IPSJ-ARC [detail] 2021-10-12
11:00
Online Online
Hiroki Kawaguchi, Yoshikazu Nagamura (Tokyo Metropolitan Univ.), Masayuki Arai (Nihon Univ.), Satoshi Fukumoto (Tokyo Metropolitan Univ.) CPSY2021-16 DC2021-16
(To be available after the conference date) [more] CPSY2021-16 DC2021-16
pp.25-30
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2021-03-26
11:00
Online Online An Estimation Method of a Defect Types for Suspected Fault Lines in Logical Faulty VLSI Using Neural Networks
Natsuki Ota, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.), Yukari Yamauchi, Masayuki Arai (Nihon Univ.) CPSY2020-61 DC2020-91
Since fault diagnosis methods for specified fault models might cause misprediction and non-prediction, a fault diagnosis... [more] CPSY2020-61 DC2020-91
pp.67-72
DC 2021-02-05
12:25
Online Online DC2020-73  [more] DC2020-73
pp.24-29
DC 2021-02-05
14:00
Online Online Multiple Target Test Generation Method using Test Scheduling Information of RTL Hardware Elements
Ryuki Asami, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ), Masayuki Arai (Nihon Univ) DC2020-74
In recent years, since the test cost for large-scale integrated circuits has increased, design-for-testability methods f... [more] DC2020-74
pp.30-35
DC, CPSY, IPSJ-ARC [detail] 2020-10-12
15:20
Online Online Note on CNN-Based Defect Location Estimation on LSI Layouts
Yoshikazu Nagamura (Tokyo Metro. Univ.), Masayuki Arai (Nihon Univ.), Satoshi Fukumoto (Tokyo Metro. Univ.) CPSY2020-20 DC2020-20
 [more] CPSY2020-20 DC2020-20
pp.16-21
CPSY, DC, IPSJ-ARC [detail] 2020-07-31
15:45
Online Online A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the number of Test Patterns
Ryuki Asami, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.) CPSY2020-12 DC2020-12
In recent years, as the high density and complexity of integrated circuits have increased, defects in cells have increas... [more] CPSY2020-12 DC2020-12
pp.75-80
HWS, VLD [detail] 2020-03-06
14:30
Okinawa Okinawa Ken Seinen Kaikan
(Cancelled but technical report was issued)
A Test Generation Method for Resistive Open Faults Using Partial MAX-SAT solver
Hiroshi Yamazaki, Yuta Ishiyama, Tatsuma Matsuta, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2019-131 HWS2019-104
In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semicon... [more] VLD2019-131 HWS2019-104
pp.215-220
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2020-02-27
14:30
Kagoshima Yoron-cho Chuou-Kouminkan Note on Dependable LoRa Transmission by Frequency and Gateway Multiplexing
Kohei Kudo, Kazuki Sasaki, Masayuki Arai (Nihon Univ.) CPSY2019-98 DC2019-104
Recently, LPWA (Low Power Wide Area) is attracting the attention as IoT-oriented communication technology, which enables... [more] CPSY2019-98 DC2019-104
pp.63-68
DC 2020-02-26
14:10
Tokyo   A Don’t Care Identification-Filling Co-Optimization Method for Low Power Testing Using Partial Max-SAT
Kenichiro Misawa, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyouto Sangyo Univ), Masayuki Arai (Nihon Univ) DC2019-92
Recently, in at-speed scan testing, excessive capture power dissipation is a serious problem. Low capture power test gen... [more] DC2019-92
pp.37-42
DC, CPSY, IPSJ-ARC [detail] 2019-06-11
14:50
Kagoshima National Park Resort Ibusuki Note on Fast SAT-Based SDN Rule Table Partitioning
Ryota Ogasawara, Masayuki Arai (Nihon Univ.) CPSY2019-4 DC2019-4
 [more] CPSY2019-4 DC2019-4
pp.39-44
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2019-03-18
09:00
Kagoshima Nishinoomote City Hall (Tanega-shima) A Test Generation Method for Resistive Open Faults Using MAX-SAT Problem
Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) CPSY2018-117 DC2018-99
In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semicon... [more] CPSY2018-117 DC2018-99
pp.315-320
DC 2019-02-27
09:00
Tokyo Kikai-Shinko-Kaikan Bldg. Note on Target Fault Selection for 2-Pattern Test Generation Considering Critical Area
Naoya Uchiyama, Masayuki Arai (Nihon Univ.) DC2018-71
 [more] DC2018-71
pp.1-5
DC 2018-12-14
14:05
Okinawa Miyako Seisyonen-No-Ie SAT-Based Solution for SDN Rule Table Partitioning
Ryota Ogasawara, Masayuki Arai (Nihon Univ.) DC2018-61
 [more] DC2018-61
pp.19-23
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-06
10:55
Hiroshima Satellite Campus Hiroshima On the Generation of Random Capture Safe Test Vectors Using Neural Networks
Sayuri Ochi, Kenichirou Misawa, Toshinori Hosokawa, Yukari Yamauchi, Masayuki Arai (Nihon Univ.) VLD2018-51 DC2018-37
Excessive capture power consumption at scan testing causes the excessive IR drop and it might cause test-induced yield l... [more] VLD2018-51 DC2018-37
pp.89-94
 Results 1 - 20 of 106  /  [Next]  
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