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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 7 of 7  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
MSS 2010-01-21
13:25
Aichi Toyota Central R&D Labs. Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme
Masafumi Onouchi, Keisuke Toyama, Toru Nojiri, Makoto Satoh (Hitachi), Masayoshi Mase, Jun Shirako (Waseda Univ.), Mikiko Sato (Tokyo Univ. of Agr and Tech.), Masashi Takada, Masayuki Ito (Renesas), Hiroyuki Mizuno (Hitachi), Mitaro Namiki (Tokyo Univ. of Agr and Tech.), Keiji Kimura, Hironori Kasahara (Waseda Univ.) CST2009-38
We developed a software-execution framework for scalable increase of execution speed and low-power consumption based on ... [more] CST2009-38
pp.7-12
ICD, IPSJ-ARC, IPSJ-EMB 2009-01-14
11:15
Osaka Shoushin Kaikan Performance Evaluation of Parallelizing Compiler Cooperated Heterogeneous Multicore Architecture Using Media Applications
Teruo Kamiyama, Yasutaka Wada, Akihiro Hayashi, Masayoshi Mase, Hirofumi Nakano, Takeshi Watanabe, Keiji Kimura, Hironori Kasahara (Waseda Univ.)
This paper describes a heterogeneous multicore architecture having accelerator cores in addition to general purpose core... [more] ICD2008-140
pp.63-68
ICD, IPSJ-ARC, IPSJ-EMB 2009-01-14
11:45
Osaka Shoushin Kaikan Local Memory Management Scheme by a Compiler for Multicore Processor
Taku Momozono, Hirofumi Nakano, Masayoshi Mase, Keiji Kimura, Hironori Kasahara (Waseda Univ.)
This paper proposes a local memory management scheme for an automatic parallelizing compiler to realize effective use o... [more] ICD2008-141
pp.69-74
ICD, IPSJ-ARC, IPSJ-EMB 2009-01-14
14:45
Osaka Shoushin Kaikan A Power Saving Scheme on Multicore Processors Using OSCAR API
Ryo Nakagawa, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara (Waseda Univ.)
Effective power reduction of an application program on multicore processors requires appropriate power control for each ... [more] ICD2008-145
pp.93-98
ICD, IPSJ-ARC 2008-05-13
10:30
Tokyo   An Evaluation of Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping
Kaito Yamada (Hitachi), Masayoshi Mase, Jun Shirako, Keiji Kimura (Waseda Univ.), Masayuki Ito, Toshihiro Hattori (Renesas), Hiroyuki Mizuno, Kunio Uchiyama (Hitachi), Hironori Kasahara (Waseda Univ.)
In order to use a large number of processor cores in a chip, hierarchical coarse grain task parallel processing, which e... [more] ICD2008-20
pp.19-24
ICD, IPSJ-ARC 2008-05-14
13:45
Tokyo   Automatic Parallelization of Restricted C Programs using Pointer Analysis
Masayoshi Mase (Waseda Univ.), Daisuke Baba (Waseda Univ. / Matsushita Electric Industrial), Harumi Nagayama (Waseda Univ. / Intel), Yuta Murata, Keiji Kimura, Hironori Kasahara (Waseda Univ.)
This paper describes a restriction on pointer usage in C language for parallelism extraction by an automatic parallelizi... [more] ICD2008-30
pp.69-74
ICD, IPSJ-ARC 2007-05-31
13:45
Kanagawa   Mutligrain Parallel Processing in SMP Execution Mode on a Multicore for Consumer Electronics
Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Hiroaki Tano, Takeshi Masuura, Takamichi Miyamoto, Jun Shirako, Hirofumi Nakano, Keiji Kimura (Waseda Univ.), Tatsuya Kamei, Toshihiro Hattori, Atsushi Hasegawa (Renesas Technology), Masaki Ito, Makoto Satoh, Kunio Uchiyama (Hitachi Ltd.)
Currently, multicore processors are becoming ubiquitous in various computing domains, namely con-
sumer electronics suc... [more]
ICD2007-21
pp.25-30
 Results 1 - 7 of 7  /   
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