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 Results 1 - 9 of 9  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM, ICD, ITE-IST [detail] 2019-08-07
13:30
Hokkaido Hokkaido Univ., Graduate School /Faculty of Information Science and [Invited Talk] A Scalable CMOS Annealing Processor for Solving Large-scale Combinatorial Optimization Problems
Masato Hayashi, Takashi Takemoto, Chihiro Yoshimura, Masanao Yamaoka (Hitachi) SDM2019-36 ICD2019-1
This paper presents a CMOS annealing processor (CMOS-AP) that accelerates ground state searches of the Ising model. The ... [more] SDM2019-36 ICD2019-1
pp.1-5
EMM 2019-01-11
11:25
Miyagi Tohoku Univ. Rotation angle estimation of watermarked regions by mode of a histogram
Masato Hayashi, Masaki Kawamura (Yamaguchi Univ.) EMM2018-89
Digital watermarks can be embedded around SIFT feature points which have invariance of geometric transform.
 When an ima... [more] EMM2018-89
pp.39-44
CAS, SIP, MSS, VLD 2018-06-15
15:45
Hokkaido Hokkaido Univ. (Frontier Research in Applied Sciences Build.) *
Sho Kanamaru, Daisuke Oku, Masashi Tawada, Shu Tanaka (Waseda Univ.), Masato Hayashi, Masanao Yamaoka (Ltd), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) CAS2018-31 VLD2018-34 SIP2018-51 MSS2018-31
(To be available after the conference date) [more] CAS2018-31 VLD2018-34 SIP2018-51 MSS2018-31
pp.161-166
EMM 2018-03-05
14:35
Kagoshima Naze Community Center (Amami-Shi, Kagoshima) [Poster Presentation] Improvement of SIFT feature-based watermarking method -- Distortion reduction of feature regions by introducing variable magnification ratio --
Masato Hayashi, Masaki Kawamura (Yamaguchi Univ.) EMM2017-78
The method of Uchida and Kawamura, which uses SIFT feature points, has two problems. 
One is that the pixel values of th... [more] EMM2017-78
pp.7-12
RECONF, CPSY, DC, IPSJ-ARC
(Joint) [detail]
2017-05-23
15:10
Hokkaido Noboribetsu-Onsen Dai-ichi-Takimoto-Kan CPSY2017-4 DC2017-4 RECONF2017-21 A CMOS Ising Computing based on Ising model, which effectively solves combinational optimization problems necessary for ... [more] CPSY2017-4 DC2017-4 RECONF2017-21
pp.15-20(CPSY), pp.15-20(DC), pp.111-116(RECONF)
COMP, IPSJ-AL 2016-06-25
13:40
Ishikawa   Contractive graph-minor embedding for CMOS Ising computer
Takuya Okuyama, Chihiro Yoshimura, Masato Hayashi, Saki Tanaka, Masanao Yamaoka (Hitachi) COMP2016-11
We proposed CMOS Ising computer, which maps the combinatorial optimization problems to the ground state search of Ising ... [more] COMP2016-11
pp.97-103
ICD 2015-04-17
14:55
Nagano   [Invited Talk] An 1800-Times-Higher Power-Efficient 20k-spin Ising Chip for Combinatorial Optimization Problem with CMOS Annealing
Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno (Hitachi) ICD2015-13
A new computing architecture using Ising model that effectively solves combinatorial optimization problems is proposed, ... [more] ICD2015-13
pp.63-68
CPM, LQE, ED 2010-11-11
10:50
Osaka   GaN growth on pseudo (111)Al substrates by RF-MBE
Tohru Honda, Masato Hayashi, Taiga Goto, Tatsuhiro Igaki (Kogakuin Univ.) ED2010-144 CPM2010-110 LQE2010-100
Fabrication of integrated light-emitting devices based on GaN requires a vertical carrier injection. In the case, GaN gr... [more] ED2010-144 CPM2010-110 LQE2010-100
pp.11-14
RCS, AN
(Joint)
2007-08-23
15:00
Niigata Niigata University Proposal and Implementation of a QoS-aware Routing Mechanism for Multi-Channel Multi-Interface Ad-Hoc Networks
Shinsuke Kajioka, Naoki Wakamiya (Osaka Univ.), Hiroki Satoh, Masato Hayashi, Susumu Matsui (Hitachi SDL), Masayuki Murata (Osaka Univ.) AN2007-24
To support real-time data transmission for audio and video communication in wireless ad-hoc networks, we propose a new r... [more] AN2007-24
pp.55-60
 Results 1 - 9 of 9  /   
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