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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 10 of 10  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, HWS
(Joint)		 2018-03-01
14:55		 Okinawa Okinawa Seinen Kaikan Core allocation with mixed multirate tasks in model-based parallelization
Yoshihiro Ikeda, Masato Edahiro (Nagoya Univ) VLD2017-114		 In recent embedded systems, multi-core processors and parallel programming are introduced to improve performance.Also, l... [more] VLD2017-114
pp.151-156
VLD, HWS
(Joint)		 2018-03-01
15:20		 Okinawa Okinawa Seinen Kaikan Hardware/Software co-design environment in model-based parallelization (MBP)
Kazuki Kashiwabara, Shinya Honda, Masato Edahiro (Nagoya Univ.) VLD2017-115		 In recent years, while the complexity and high performance of in-vehicle systems are progressing, restrictions on time a... [more] VLD2017-115
pp.157-162
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-28
08:55		 Kagoshima   System-level design method considering the interrupt processing
Yuki Ando, Yukihito Ishida, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ.) VLD2013-77 DC2013-43		 We propose a system level design methodology for control systems that have both input and output by abstraction of inter... [more] VLD2013-77 DC2013-43
pp.119-124
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-28
10:25		 Kagoshima   Automatic synthesis of the inter-processor communication implimentation for hetero multiprocessor systems
Yukihito Ishida, Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ.) RECONF2013-50		 This paper introduces an automatic synthesis technique of inter-processor communication for System-on-chip with heteroge... [more] RECONF2013-50
pp.63-68
VLD 2013-03-05
13:00		 Okinawa Okinawa Seinen Kaikan [Invited Talk] Cyber-Physical Systems and LSI Design Technologies
Shinpei Kato, Masato Edahiro (Nagoya Univ.) VLD2012-147		 Our society faces a core challenge to societal problems, including environmental pollution and aging population , and in... [more] VLD2012-147
pp.67-69
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-17
13:25		 Kanagawa   A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs
Krzysztof Jozwik, Shinya Honda, Masato Edahiro (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.) VLD2012-130 CPSY2012-79 RECONF2012-84		 Dynamically Partially Reconfigurable (DPR) FPGAs allow for implementation of a concept of SW-HW multitasking where flow ... [more] VLD2012-130 CPSY2012-79 RECONF2012-84
pp.135-140
COMP 2012-06-21
15:40		 Hokkaido Hokkaido University Optimal Average Joint Hamming Weight for Asymmetric Representation
Vorapong Suppakitpaisarn (Univ. of Tokyo), Masato Edahiro (Nagoya Univ.), Hiroshi Imai (Univ. of Tokyo) COMP2012-22		  [more] COMP2012-22
pp.79-86
RECONF 2012-05-29
16:45		 Okinawa Tiruru (Naha Okinawa, Japan) Implementation and evaluation of the AES/ADPCM on STP and FPGA with Behavioral Synthesis
Yukihito Ishida, Seiya Shibata, Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ) RECONF2012-14		 Reconfigurable techniques are attracting attention as an alternative to dedicated hardware of SoC.
We have evaluated FP... [more]		 RECONF2012-14
pp.77-82
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] 2011-03-19
14:45		 Okinawa   Parallel C code generation from Simulink models
Takahiro Kumura (NEC/Osaka Univ.), Masato Edahiro, Yuichi Nakamura (NEC), Nagisa Ishiura (Kwansei Gakuin Univ.), Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) CPSY2010-80 DC2010-79		 This paper proposes a method to generate parallel C code from
models developed on the Simulink which is a model-based
... [more]		 CPSY2010-80 DC2010-79
pp.303-308
ICD, SDM 2007-08-23
11:35		 Hokkaido Kitami Institute of Technology A Periodically All-in-Phase Clocking Architecture for Multi-Core SOC Platforms
Atsufumi Shibayama, Koichi Nose, Sunao Torii, Masayuki Mizuno, Masato Edahiro (NEC) SDM2007-147 ICD2007-75		 Methods for clock generation, distribution, and synchronization in system-on-chip (SOC) designs have become important is... [more] SDM2007-147 ICD2007-75
pp.35-40
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