Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
SR |
2016-01-21 13:55 |
Nagasaki |
Fukue-bunka-kaikan |
[Invited Talk]
Trend and NEC's Activities for Mobile Edge Computing Toshiki Takeuchi, Takanori Iwai, Masao Ikekawa (NEC) SR2015-74 |
In recent years, the research activities toward the fifth-generation wireless systems (5G) has become active in the mobi... [more] |
SR2015-74 p.17 |
RCC, ASN, RCS, NS, SR (Joint) |
2015-07-30 13:00 |
Nagano |
JA Naganoken Bldg. |
[Invited Talk]
Research and Development of Small Cell Base Station for 5G Network Naoto Ishii, Yi Jiang, Yasushi Maruta, Kazuaki Kunihiro, Masao Ikekawa (NEC) RCC2015-36 NS2015-56 RCS2015-119 SR2015-37 ASN2015-46 |
Much attention from industry and academia in the move from current cellular systems toward 5G are attractive since recen... [more] |
RCC2015-36 NS2015-56 RCS2015-119 SR2015-37 ASN2015-46 pp.105-110(RCC), pp.109-114(NS), pp.107-112(RCS), pp.123-128(SR), pp.145-150(ASN) |
SR |
2011-07-29 13:45 |
Kanagawa |
YRP |
[Invited Talk]
A Programmable Signal Processing Accelerator for Flexible LTE Base Stations Masao Ikekawa (NEC) SR2011-41 |
High flexibility as well as high performance is desired for the wireless base stations to support rapid evolution of wir... [more] |
SR2011-41 p.151 |
RECONF |
2011-05-13 13:30 |
Hokkaido |
Hokkaido Univ. (Faculty of Eng., B3 Bldg.) |
A Implementation of Programmable Re-Ordering Unit for Array Processor Tomoyoshi Kobori, Nozomi Ishihara, Katsutoshi Seki, Masao Ikekawa (NEC) RECONF2011-18 |
We present a novel re-ordering unit architecture for array processor. In novel re-ordering unit, memory architecture is ... [more] |
RECONF2011-18 pp.103-108 |
VLD |
2009-03-11 10:30 |
Okinawa |
|
Optimum Code Scheduling for VLIW DSP SPXK5 considering Conditional Execution Tetsuya Yamamoto, Nagisa Ishiura (Kwansei Gakuin Univ.), Takahiro Kumura, Masao Ikekawa (NEC), Masaharu Imai (Osaka Univ.) VLD2008-126 |
This article presents an optimum code scheduling method for digital signal processor SPXK5 taking account of its archite... [more] |
VLD2008-126 pp.1-6 |
SR |
2008-07-31 13:55 |
Tokyo |
NICT (Koganei,-city Tokyo) |
An efficient memory access system for array processor in wireless comunication system Tomoyoshi Kobori, Katsutoshi Seki, James Okello, Masao Ikekawa (NEC) SR2008-23 |
This paper describes the efficient memory access system for array processor in wireless communication system. Today, the... [more] |
SR2008-23 pp.37-42 |
SR |
2008-01-25 09:00 |
Nagano |
Tateyama Prince hotel (Ohmachi city, Nagano prefecture) |
A CORDIC-BASED RECONFIGURABLE SYSTOLIC ARRAY PROCESSOR FOR MIMO-OFDM WIRELESS COMMUNICATIONS Katsutoshi Seki, Tomoyoshi Kobori, James Okello, Masao Ikekawa (NEC) SR2007-72 |
A reconfigurable systolic array processor based on a coordinate rotation digital computer (CORDIC) algorithm is proposed... [more] |
SR2007-72 pp.37-42 |
SR |
2008-01-25 09:25 |
Nagano |
Tateyama Prince hotel (Ohmachi city, Nagano prefecture) |
Interference Mitigation for WCDMA Using a QR Decomposition and a CORDIC-based Reconfigurable Systolic Array Robin Scheibler (Seiss Federal Inst. of Tech.), James Okello, Katsutoshi Seki, Tomoyoshi Kobori, Masao Ikekawa (NEC) SR2007-73 |
This paper presents implementation and performance of QR Decomposition based Recursive Least-
-Squares (QRD-RLS) for in... [more] |
SR2007-73 pp.43-48 |
SR |
2008-01-25 09:50 |
Nagano |
Tateyama Prince hotel (Ohmachi city, Nagano prefecture) |
FFT with Reduced Complexity and Its Application to a CORDIC-Based Reconfigurable Systolic Array James Okello, Katsutoshi Seki, Tomoyoshi Kobori, Masao Ikekawa (NEC) SR2007-74 |
[more] |
SR2007-74 pp.49-54 |
RECONF, CPSY, VLD, IPSJ-SLDM |
2008-01-17 16:50 |
Kanagawa |
Hiyoshi Campus, Keio University |
VLIW Extension of Software Development Environment Construction Tool ArchC Takanori Morimoto (Kwansei Gakuin Univ.), Takahiro Kumura (NEC), Nagisa Ishiura (Kwansei Gakuin Univ.), Masao Ikekawa (NEC), Masaharu Imai (Osaka Univ.) VLD2007-134 CPSY2007-77 RECONF2007-80 |
ArchC is a C++/SystemC-based open-source software,which generates software development environments (consisting of Binut... [more] |
VLD2007-134 CPSY2007-77 RECONF2007-80 pp.95-100 |
SIP, CAS, CS |
2007-03-06 09:30 |
Tottori |
Blancart Misasa (Tottori) |
[Poster Presentation]
The Co-operated System between FPGA Emulator and MATLAB Tomoyoshi Kobori, Katsutoshi Seki, James Okello, Masao Ikekawa (NEC) CAS2006-99 SIP2006-200 CS2006-116 |
This paper presents the co-operated system between FPGA emulator and MATLAB. In the field of SoC development, the evalua... [more] |
CAS2006-99 SIP2006-200 CS2006-116 pp.35-36 |
SR |
2006-07-27 14:00 |
Kanagawa |
YRP |
[Technology Exhibit]
An evaluation of DRP in the development of mobile BTS baseband LSI Tomoyoshi Kobori, Masao Ikekawa (NEC) SR2006-32 |
In this paper, we describe the performance evaluation of baseband processing in mobile BTS with DRP. In the baseband pro... [more] |
SR2006-32 pp.127-132 |
RCS, AP, WBS, MW, MoNA |
2005-03-03 10:00 |
Kanagawa |
Yokosuka Research Park |
A Complete Blind MIMO Equalizer for Wireless Communication System James Okello, Masao Ikekawa (NEC) |
[more] |
WBS2004-107 AP2004-288 RCS2004-375 MoMuC2004-158 MW2004-285 pp.51-56 |