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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2023-04-10 15:15 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Invited Talk]
Prospects for Next-Generation Edge Computing Based on Nonvolatile Logic LSI Technology Masanori Natsui (Tohoku Univ.)  ICD2023-6 |
[more] | ICD2023-6 p.14 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-02 14:45 |
Online | Online | Operating-Condition-Aware Power-Gating-Switch Control Technique and Its Application to Nonvolatile Logic LSI Fangcen Zhong, Masanori Natsui, Takahiro Hanyu (Tohoku Univ.) VLD2021-47 ICD2021-57 DC2021-53 RECONF2021-55 |
[more] | VLD2021-47 ICD2021-57 DC2021-53 RECONF2021-55 pp.172-177 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2020-11-17 09:55 |
Online | Online | A Study on Power Gating Switch Control Technique for Nonvolatile Logic LSI Fangcen Zhong, Masanori Natsui, Takahiro Hanyu (Tohoku Univ.) VLD2020-12 ICD2020-32 DC2020-32 RECONF2020-31 |
[more] | VLD2020-12 ICD2020-32 DC2020-32 RECONF2020-31 pp.6-11 |
| VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-14 15:05 |
Ehime | Ehime Prefecture Gender Equality Center | Design of an MTJ-Based Multiply-Accumulate Operation Circuit for an Energy-Efficient Binarized Neural Networks Tomoki Chiba, Masanori Natsui, Takahiro Hanyu (Tohoku Univ.) ICD2019-32 IE2019-38 |
In this paper, we propose a design of a computational unit for multiply-accumulate (MAC) operations and activation funct... [more] | ICD2019-32 IE2019-38 pp.19-24 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 15:20 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Prospects of an Error-Correction Technique of Intra-Chip Data Transmission Using Time-Series Feature Kentaro Kato, Masanori Natsui, Takahiro Hanyu (Tohoku Univ.) CPM2017-85 ICD2017-44 IE2017-70 |
This paper presents a top-down error-correction technique of intra-chip data transmission using time-series feature extr... [more] | CPM2017-85 ICD2017-44 IE2017-70 pp.33-38 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 13:20 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Design of High-Speed Low-Power Analog-to-Digital Converter for a Nonvolatile Micro-controller
-- High-Speed Low-Power Reference-Less SAR-ADC -- Tamakoshi Akira, Masanori Natsui, Takahiro Hanyu (Touhoku Univ.) CPM2016-86 ICD2016-47 IE2016-81 |
A high-speed low-power successive-approximation-type analog-to-digital converter (SAR ADC) is proposed for a key module ... [more] | CPM2016-86 ICD2016-47 IE2016-81 pp.51-56 |
| ICD | 2015-04-17 13:55 |
Nagano | [Tutorial Lecture]
Nonvolatile Logic-in-Memory Architecture and Its Applications to Low-Power VLSI System Takahiro Hanyu, Daisuke Suzuki, Akira Mochizuki, Masanori Natsui, Naoya Onizawa (Tohoku Univ.), Tadahiko Sugibayashi (NEC), Shoji Ikeda, Tetsuo Endoh, Hideo Ohno (Tohoku Univ.) ICD2015-12 |
[more] | ICD2015-12 pp.57-61 |
|
| ICD | 2014-04-17 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
Fabrication of a 99%-Energy-Less Nonvolatile Multi-Functional CAM Chip Using Hierarchical Power Gating for a Massively-Parallel Full-Text-Search Engine Shoun Matsunaga (Tohoku Univ.), Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi (NEC), Masanori Natsui, Akira Mochizuki, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu (Tohoku Univ.) ICD2014-8 |
We demonstrate a 1-Mb nonvolatile TCAM-based search engine using 90-nm CMOS and perpendicular MTJ technologies for an ul... [more] | ICD2014-8 pp.39-44 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 13:25 |
Kagoshima | A Method for Optimizing Power-Efficiency of an MTJ-Based Nonvolatile FPGA Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Takahiro Hanyu (Tohoku Univ.) CPM2013-116 ICD2013-93 |
In this paper, a design methodology for realizing power efficient nonvolatile FPGA (NVFPGA) using magnetic tunnel juncti... [more] | CPM2013-116 ICD2013-93 pp.49-53 |
|
| ICD | 2010-04-22 15:20 |
Kanagawa | Shonan Institute of Tech. | Fabrication of a Nonvolatile Lookup-Table Circuit Chip Using Magneto/Semiconductor-Hybrid Structure for an Immediate-Power-Up Field Programmable Gate Array Daisuke Suzuki, Masanori Natsui, Shoji Ikeda (Tohoku Univ.), Haruhiro Hasegawa, Katsuya Miura, Jun Hayakawa (ARL, Hitachi, Ltd.), Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu (Tohoku Univ.) ICD2010-9 |
This paper presents a nonvolatile LUT (Lookup-Table) circuit in FPGA (Field-Programmable Gate Array) using a MTJ (Magnet... [more] | ICD2010-9 pp.47-52 |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 10:05 |
Kanagawa | Improvement of Search Efficiency by Principal Component Analysis for Analog Circuit Sizing of Operational Amplifier using Genetic Algorithm Yuji Takehara (Toyohashi Univ. Tech.), Masanori Natsui (Tohoku Univ.), Yoshiaki Tadokoro (Toyohashi Univ. Tech.) VLD2008-112 CPSY2008-74 RECONF2008-76 |
This paper presents an automatic sizing of analog circuits using genetic algorithm (GA) and its performance improvement ... [more] | VLD2008-112 CPSY2008-74 RECONF2008-76 pp.123-128 |
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