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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 11 of 11  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, IPSJ-SLDM 2008-05-09
11:40
Hyogo Kobe Univ. Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption
Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) VLD2008-9
This paper describes analysis of on-chip bus power in the presence of arrival time variations of input signals. With shr... [more] VLD2008-9
pp.13-18
DC, CPSY, IPSJ-SLDM, IPSJ-EMB 2008-03-27
08:45
Kagoshima   An Adaptive Multi-Performance Processor and its Evaluation
Seiichiro Yamaguchi, Yuichiro Oyama (Kyushu Univ.), Yuji Kunitake (Kyushu Inst. of Tech.), Tadayuki Matsumura, Yuriko Ishitobi, Masaki Yamaguchi, Donghoon Lee, Yusuke Kaneda (Kyushu Univ.), Toshimasa Funaki (Kyushu Inst. of Tech.), Masanori Muroyama, Tohru Ishihara, Toshinori Sato (Kyushu Univ.) DC2007-84 CPSY2007-80
This paper presents an energy efficient processor which can be used as a design alternative for the dynamic voltage scal... [more] DC2007-84 CPSY2007-80
pp.1-6
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2007-11-20
10:05
Fukuoka Kitakyushu International Conference Center A Memory Management Technique for Energy Reduction in Multi-Task Embedded Applications
Seiichiro Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.)
Memory systems consume a significant amount of the energy in embedded systems. Static code placement techniques using sc... [more] VLD2007-74 DC2007-29
pp.25-29
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2007-11-20
15:35
Fukuoka Kitakyushu International Conference Center An On-Chip Bus Architecture for Post-Fabrication Timing Calibration
Masaki Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.)
As the transistor size shrinks, the horizontal coupling capacitance between adjacent wires becomes dominant for wire loa... [more] VLD2007-79 DC2007-34
pp.55-60
ICD, VLD 2007-03-07
17:20
Okinawa Mielparque Okinawa A Gate Sizing Technique for Maximizing Timing Yield of CMOS Circuits
Ryota Sakamoto, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.)
 [more] VLD2006-117 ICD2006-208
pp.67-72
ICD, VLD 2007-03-07
17:40
Okinawa Mielparque Okinawa A Study of Dependence on Gate Depth/Width for Analyzing Delay/Power Variations in 90nm CMOS Circuits
Masaki Yamaguchi (Kyushu Univ.), Yuan Yang (Xi’an Univ. of Technology), Ryota Sakamoto, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.)
As the transistor size shrinks, process variations increase. Under the existence of the variations, an existing design f... [more] VLD2006-118 ICD2006-209
pp.73-78
RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2006-11-28
09:25
Fukuoka Kitakyushu International Conference Center A Study on Energy Reduction in Quality-driven Digital Wireless Communication Systems
Masayuki Tokunaga (Kyushu Univ), Taizo Tsujimoto (FLEETS), Hiroto Yasuura, Masanori Muroyama (Kyushu Univ)
 [more] CPSY2006-35
pp.7-12
VLD, IPSJ-SLDM 2006-05-11
15:00
Ehime Ehime University A Software-level Energy Reduction Technique for Embedded Microprocessor Exploiting Narrow Bitwidth Operations
Seiichiro Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.)
This paper proposes a software-level energy reduction technique for microprocessor-based embedded systems. A basic idea ... [more] VLD2006-3
pp.13-18
VLD, IPSJ-SLDM 2006-05-12
14:00
Ehime Ehime University Measurement and Analysis of Delay and Power Variations in 90nm CMOS Circuits
Masaki Yamaguchi (Kyushu Univ.), Yang Yuan (Xi'an Univ. of Technology), Kosuke Tarumi, Ryota Sakamoto, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.)
As the transistor size shrinks, process variations increase. Under the existence of the variations, an existing design f... [more] VLD2006-13
pp.41-46
SIP, ICD, IE, IPSJ-SLDM 2005-10-21
14:00
Miyagi Ichinobo, Sakunami-Spa A Reliability Evaluation Technique for Soft-Error Susceptible Computer Systems
Makoto Sugihara (ISIT), Tohru Ishihara (Kyushu Univ.), Koji Hashimoto (Fukuoka Univ.), Masanori Muroyama (Kyushu Univ.)
As the feature size of integrated circuits shrinks, their voltage and noise margins are lowered and the soft error issue... [more] SIP2005-123 ICD2005-142 IE2005-87
pp.49-54
ICD, SDM 2005-08-18
09:45
Hokkaido HAKODATE KOKUSAI HOTEL A Digital Detector Design For Measuring Gate-Delay Variation
Ryota Sakamoto, Masanori Muroyama, Kosuke Tarumi, Hiroto Yasuura (Kyushu Univ.)
(Advance abstract in Japanese is available) [more] SDM2005-131 ICD2005-70
pp.19-24
 Results 1 - 11 of 11  /   
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