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Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF 2005-05-12
10:30
Kyoto Kyoto University Execution Cycle Minimization Algorithm for Dynamic Reconfigurable Processors with Hierarchical Memory Structure
Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.)
The dynamic reconfigurable processor is a device that can change interconnections between processor elements and process... [more] RECONF2005-3
pp.13-18
IE, SIP, ICD, IPSJ-SLDM 2004-10-22
15:50
Yamagata   Bus architecture optimization method for IP-based design
Kyoko Ueda, Keishi Sakanushi, Noboru Yoneoka, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.)
In IP-based design, to find the optimal bus architecture is very important problem because bus architecture strongly aff... [more] SIP2004-101 ICD2004-133 IE2004-77
pp.73-78
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