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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF 2021-06-09
Online Online [Invited Talk] Large-scale combinatorial optimization in real-time systems by FPGA-based accelerators for simulated bifurcation
Kosuke Tatsumura (TOSHIBA) RECONF2021-11
Combinatorial optimization problems are economically valuable but computationally hard to solve. Many practical combinat... [more] RECONF2021-11
ICD 2017-04-21
Tokyo   [Invited Lecture] High-Density User-Programmable Logic Array Based on Adjacent Integration of Pure-CMOS Crossbar Antifuse into Logic CMOS Circuits
Shinichi Yasuda, Masato Oda, Mari Matsumoto, Kosuke Tatsumura, Koichiro Zaitsu, Ying-Hao Ho, Mizuki Ono (Toshiba) ICD2017-15
 [more] ICD2017-15
SDM 2015-10-29
Miyagi Niche, Tohoku Univ. [Invited Talk] Low-power and high-speed FPGA by adjacent integration of flash memory and CMOS logic
Koichiro Zaitsu, Kosuke Tatsumura, Mari Matsumoto, Masato Oda, Shinichi Yasuda (Toshiba) SDM2015-75
Novel nonvolatile programmable switch for low-power and high-speed FPGA where flash memory is adjacently integrated to C... [more] SDM2015-75
ICD, SDM 2014-08-05
Hokkaido Hokkaido Univ., Multimedia Education Bldg. [Invited Talk] Low-Power and High-Speed Nonvolatile FPGA by Adjacent Integration of MONOS/Logic and Novel Programming Scheme
Koichiro Zaitsu, Kosuke Tatsumura, Mari Matsumoto, Masato Oda, Shinobu Fujita, Shinichi Yasuda (Toshiba) SDM2014-75 ICD2014-44
Novel nonvolatile programmable switch for low-power and high-speed FPGA where MONOS flash is adjacently integrated to CM... [more] SDM2014-75 ICD2014-44
SDM 2012-11-15
Tokyo Kikai-Shinko-Kaikan Bldg Neutral and Attractive Traps in Random Telegraph Signal Noise Phenomena using (100)- and (110)-Oriented CMOSFETs
Jiezhi Chen, Izumi Hirano, Kosuke Tatsumura, Yuichiro Mitani (Toshiba Corp) SDM2012-103
(To be available after the conference date) [more] SDM2012-103
ICD, SDM 2009-07-16
Tokyo Tokyo Institute of Technology The Study of Mobility-Tinv Trade-off in Deeply Scaled High-k/Metal Gate Devices and Scaling Design Guideline for 22nm-node Generation
Masakazu Goto, Shigeru Kawanaka, Seiji Inumiya, Naoki Kusunoki, Masumi Saitoh, Kosuke Tatsumura, Atsuhiro Kinoshita, Satoshi Inaba, Yoshiaki Toyoshima (Toshiba) SDM2009-107 ICD2009-23
The trade-off between Tinv scaling and carrier mobility () degradation in deeply scaled HK/MG nMOSFETs has been ... [more] SDM2009-107 ICD2009-23
SDM 2009-06-19
Tokyo An401・402 Inst. Indus. Sci., The Univ. of Tokyo Intrinsic Correlation between Mobility Reduction and Vt shift due to Interface Dipole Modulation in HfSiON/SiO2 stack by La or Al addition
Kosuke Tatsumura, Takamitsu Ishihara, Seiji Inumiya, Kazuaki Nakajima, Akio Kaneko, Masakazu Goto, Shigeru Kawanaka, Atsuhiro Kinoshita (Toshiba Corp.) SDM2009-39
Intrinsic correlation between mobility reduction by remote Coulomb scattering (RCS) and threshold voltage shift (ΔVt), b... [more] SDM2009-39
ICD, SDM 2008-07-18
Tokyo Kikai-Shinko-Kaikan Bldg. Impact of Tantalum Composition in TaCx/HfSiON Gate Stack on Device Performance of Aggressively Scaled CMOS Devices with SMT and Strained CESL
Masakazu Goto, Kosuke Tatsumura, Shigeru Kawanaka, Kazuaki Nakajima, Reika Ichihara, Yasuhito Yoshimizu, Hiroyuki Onoda, Koji Nagatomo, Toshiyuki Sasaki, Takashi Fukushima, Akiko Nomachi, Seiji Inumiya, Tomonori Aoyama, Masato Koyama, Yoshiaki Toyoshima (Toshiba Corp.) SDM2008-147 ICD2008-57
We report TaCx/HfSiON gate stack CMOS device with simplified gate 1st process from the viewpoints of fixed charge genera... [more] SDM2008-147 ICD2008-57
ICD, SDM 2007-08-24
Hokkaido Kitami Institute of Technology [Special Invited Talk] Effect of metal-gate/high-k on characteristics of MOSFETs for 32nm CMOS and beyond
Masato Koyama, Masahiro Koike, Yuuichi Kamimuta, Masamichi Suzuki, Kosuke Tatsumura, Yoshinori Tsuchiya, Reika Ichihara, Masakazu Goto, Koji Nagatomo, Atsushi Azuma, Shigeru Kawanaka, Kazuaki Nakajima, Katsuyuki Sekine (Toshiba Corp.) SDM2007-159 ICD2007-87
In this paper, influences of metal-gate and high-k gate dielectric application on MOSFET (32nm node and beyond) characte... [more] SDM2007-159 ICD2007-87
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