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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 21  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM 2020-11-20
16:40
Online Online [Invited Talk] TCAD simulation for atomic layer channel Tunnel FETs based on ab-initio band calculation
Hiderhiro Asai (AIST), Tatsuya Kuroda (Osaka Univ.), Koichi Fukuda, Junichi Attori, Tsutomu Ikegami (AIST), Nobuya Mori (Osaka Univ.) SDM2020-34
 [more] SDM2020-34
pp.58-62
SDM 2019-11-08
09:30
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Device Simulation of Dynamic Behavior of Ferroelectric Field-Effect Transistors
Junichi Hattori, Tsutomu Ikegami, Koichi Fukuda, Hiroyuki Ota, Shinji Migita, Hidehiro Asai (AIST) SDM2019-74
We propose a method to simulate the dynamic behavior of field-effect transistors (FETs) having ferroelectric materials i... [more] SDM2019-74
pp.27-32
SDM 2019-01-29
09:30
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Multidomain Dynamics of Ferroelectric Polarization in Negative Capacitance State and its Impacts on Performances of Field-Effect Transistors
Hiroyuki Ota, Tsutomu Ikegami, Koichi Fukuda, Junichi HattoriI, Hidehiro Asai, Kazuhiko Endo, Shinji Migita (AIST), Akira Toriumi (The Univ. of Tokyo) SDM2018-81
In this paper, we clarified the multidomain dynamics of ferroelectric polarization in the Negative Capacitance Field-Eff... [more] SDM2018-81
pp.1-4
SDM 2018-11-09
14:20
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Device Simulation of Field-Effect Transistor Using Ferroelectric Negative Capacitance
Junichi Hattori, Tsutomu Ikegami, Koichi Fukuda, Hiroyuki Ota, Shinji Migita, Hidehiro Asai (AIST) SDM2018-74
We consider the method to simulate negative-capacitance field-effect transistors (NC FETs) harnessing negative capacitan... [more] SDM2018-74
pp.47-52
SDM 2018-01-30
11:00
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Perspective of Negative Capacitance FinFETs Investigated by Transient TCAD Simulation
Hiroyuki Ota, Shinji Mgita, Tsutomu Ikegami, Junichi Hattori, Hidehiro Asai, Koichi Fukuda (AIST), Akira Toriumi (The Univ. of Tokyo) SDM2017-91
 [more] SDM2017-91
pp.1-4
SDM 2017-11-09
15:40
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] GaN MOS capacitance simulation considering deep traps
Koichi Fukuda, Hidehiro Asai, Junichi Hattori, Mitsuaki Shimizu (AIST), Tamotsu Hashizume (Hokkaido Univ.) SDM2017-66
Transient mode device simulation is applied to obtain capacitances of GaN MOS capacitors including deep level traps, and... [more] SDM2017-66
pp.27-32
SDM, ICD, ITE-IST [detail] 2017-07-31
12:00
Hokkaido Hokkaido-Univ. Multimedia Education Bldg. TCAD Simulation of C-TFET Circuit with Drain Offset Structure
Hidehiro Asai, Takahiro Mori, Junich Hattori, Koichi Fukuda, Kazuhiko Endo, Takashi Matsukawa (AIST) SDM2017-35 ICD2017-23
We have performed TCAD simulation for a ring oscillator composed of complementary Tunnel Field Effect Transistors (C-TFE... [more] SDM2017-35 ICD2017-23
pp.21-24
SDM 2017-02-06
13:35
Tokyo Tokyo Univ. [Invited Talk] Electrical coupling of stacked transistors in monolithic three-dimensional inverters and its dependence on the interlayer dielectric thickness
Junichi Hattori, Koichi Fukuda, Toshifumi Irisawa, Hiroyuki Ota, Tatsuro Maeda (AIST) SDM2016-143
We study the electrical coupling of stacked transistors in monolithic three-dimensional (3D) inverters and investigate i... [more] SDM2016-143
pp.23-28
SDM 2017-01-30
10:00
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Demonstrating Performance Improvement of Complementary TFET Circuits by ION Enhancement Based on Isoelectronic Trap Technology
Takahiro Mori, Hidehiro Asai, Junichi Hattori, Koichi Fukuda, Shintaro Otsuka, Yukinori Morita, Shin-ichi O'uchi, Hiroshi Fuketa, Shinji Migita, Wataru Mizubayashi, Hiroyuki Ota, Takashi Matuskawa (ANational Institute of Advanced Industrial ScieIST) SDM2016-130
We improved the performance of a complementary circuit comprising Si-based tunnel field-effect transistors (TFETs) by us... [more] SDM2016-130
pp.1-4
SDM 2017-01-30
11:30
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Fully Coupled 3-D Device Simulation of Negative Capacitance FinFETs for Sub 10 nm Integration
Hiroyuki Ota, Tsutomu Ikegami, Junichi Hattori, Koichi Fukuda, Shinji Migita (AIST), Akira Toriumi (The Univ. of Tokyo) SDM2016-133
Subthreshold operation of negative capacitance FinFETs (NC-FinFETs) at sub 10 nm gate length are analyzed with a newly d... [more] SDM2016-133
pp.13-16
SDM 2016-06-29
10:40
Tokyo Campus Innovation Center Tokyo [Invited Lecture] Design of SOI-FETs for Steep Slope Switching using Negative Capacitance in Ferroelectric Gate Insulators
Hiroyuki Ota, Shinji Migita, Junichi Hattori, Koichi Fukuda (AIST), Akira Toriumi (The Univ. of Tokyo) SDM2016-34
This paper discusses a design of fully depleted silicon-on-insulator field-effect transistors with ferroelectric gate in... [more] SDM2016-34
pp.9-13
SDM 2016-01-28
11:00
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Understanding of BTI for Tunnel FETs
Wataru Mizubayashi, Takahiro Mori, Koichi Fukuda, Yuki Ishikawa, Yukinori Morita, Shinji Migita, Hiroyuki Ota, Yongxun Liu, Shinichi O'uchi, Junichi Tsukada, Hiromi Yamauchi, Takashi Matsukawa, Meishoku Masahara, Kazuhiko Endo (AIST) SDM2015-122
(To be available after the conference date) [more] SDM2015-122
pp.9-12
SDM 2015-01-27
15:30
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Accurate Prediction of PBTI Lifetime in N-type Fin-Channel High-k Tunnel FETs
Wataru Mizubayashi, Takahiro Mori, Koichi Fukuda, Yongxun Liu, Takashi Matsukawa, Yuki Ishikawa, Kazuhiko Endo, Shinichi Ohuchi, Junichi Tsukada, Hiromi Yamauchi, Yukinori Morita, Shinji Migita, Hiroyuki Ota, Meishoku Masahara (AIST) SDM2014-143
The positive bias temperature instability (PBTI) characteristics for n-type fin-channel tunnel FETs (TFETs) with high-k ... [more] SDM2014-143
pp.33-36
SDM 2015-01-27
16:20
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Scaling Breakthrough for Analog/Digital Circuits by Suppressing Variability and Low-Frequency Noise for FinFETs by Amorphous Metal Gate Technology
Takashi Matsukawa, Koichi Fukuda, Yongxun Liu, Junichi Tsukada, Hiromi Yamauchi, Yuki Ishikawa, Kazuhiko Endo, Shinichi O'uchi, Shinji Migita, Wataru Mizubayashi, Yukinori Morita, Hiroyuki Ota, Meishoku Masahara (AIST) SDM2014-145
 [more] SDM2014-145
pp.41-44
SDM 2015-01-27
16:45
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Experimental Realization of Complementary p- and n- Tunnel FinFETs with Subthreshold Slopes of Less than 60 mV/decade and Very Low (pA/um) Off-Current on a Si CMOS Platform
Yukinori Morita, Takahiro Mori, Koichi Fukuda, Wataru Mizubayashi, Shinji Migita, Takashi Matsukawa, Kazuhiko Endo, Shinichi O'uchi, Yongxun Liu, Meishoku Masahara, Hiroyuki Ota (AIST) SDM2014-146
Complementary (p- and n-type) tunnel FinFETs operating with subthreshold slopes (SSs) of less than 60 mV/decade and very... [more] SDM2014-146
pp.45-48
ICD, SDM 2014-08-04
13:05
Hokkaido Hokkaido Univ., Multimedia Education Bldg. [Invited Talk] Research progress in steep slope devices and technologies to enhance ON current in TFETs
Takahiro Mori, Yukinori Morita, Shinji Migita, Wataru Mizubayashi, Koichi Fukuda, Noriyuki Miyata, Tetsuji Yasuda, Meishoku Masahara, Hiroyuki Ota (AIST) SDM2014-67 ICD2014-36
Steep slope devices (SSDs) have attracted because of the increase demand for low-power devices. This paper reviews recen... [more] SDM2014-67 ICD2014-36
pp.29-34
SDM, ICD 2013-08-01
09:25
Ishikawa Kanazawa University Performance Enhancement of Tunnel Field-Effect Transistors by Synthetic Electric Field Effect
Yukinori Morita, Takahiro Mori, Shinji Migita, Wataru Mizubayashi, Akihito Tanabe, Koichi Fukuda, Kazuhiko Endo, Takashi Matsukawa, Shin-ichi O'uchi, Yongxun Liu, Meishoku Masahara, Hiroyuki Ota (AIST) SDM2013-66 ICD2013-48
A synthetic electric field effect to enhance the performance of tunnel field-effect transistors (TFETs) is proposed. The... [more] SDM2013-66 ICD2013-48
pp.7-12
SDM 2012-11-16
14:15
Tokyo Kikai-Shinko-Kaikan Bldg Nonlocal band to band tunneling model for tunnel-FETs -- Device and circuit models --
Koichi Fukuda, Takahiro Mori, Wataru Mizubayashi, Yukinori Morita, Akihito Tanabe, Meishoku Masahara, Tetsuji Yasuda, Shinji Migita, Hiroyuki Ota (AIST) SDM2012-111
Device and compact models for tunnel-FETs are developed based on nonlocal band to band tunneling model. For device model... [more] SDM2012-111
pp.63-68
SDM 2011-11-10
14:40
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Device Simulation of STM Carrier Profiling
Koichi Fukuda, Masayasu Nishizawa, Tetsuya Tada (AIST), Leonid Bolotov (Tsukuba Univ.), Kaina Suzuki, Shigeo Sato (Fujitsu Semiconductor), Hiroshi Arimoto, Toshihiko Kanayama (AIST) SDM2011-119
 [more] SDM2011-119
pp.21-26
ICD 2011-04-18
13:30
Hyogo Kobe University Takigawa Memorial Hall [Invited Talk] Technology Trend of NAND Flash Memories -- A 151mm2 64Gb 2b/cell NAND Flash Memory in 24nm CMOS Technology --
Koichi Fukuda, Yoshihisa Watanabe, Eiichi Makino, Koichi Kawakami, Junpei Sato, Teruo Takagiwa, Naoaki Kanagawa, Hitoshi Shiga, Naoya Tokiwa, Yoshihiko Shindo, Toshiaki Edahiro, Takeshi Ogawa, Makoto Iwai (Toshiba), Kiyofumi Sakurai (Toshiba Memory Systems), Toru Miwa (SanDisk) ICD2011-4
A 64Gbit 2bit/cell NAND flash memory capable of 14MB/s programming and 266MB/s data transfer is fabricated in 24nm techn... [more] ICD2011-4
pp.19-26
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