IEICE Technical Committee Submission System
Conference Schedule		 Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 5 of 5  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM 2016-06-29
15:05		 Tokyo Campus Innovation Center Tokyo Effects of ultraviolet irradiation on the band offset of Tantalum nanosheets/SiO2/Si interfaces
Shuhei Hayami, Satoshi Toyoda, Katsutoshi Fukuda (Kyoto Univ.), Hidetaka Sugaya (Panasonic), Masahito Morita, Akiyoshi Nakata, Yoshiharu Uchimoto, Eiichiro Matsubara (Kyoto Univ.) SDM2016-42		 On the basis of material design for ReRAM, the interfacial band offset between insulators and Si substrate is one of the... [more] SDM2016-42
pp.53-58
CPM, EE 2012-02-10
15:35		 Tokyo Kikai-Shinko-Kaikan Bldg Effect of Zinc Surface Modification on Electrochemical Properties for Alkaline Zn-based Secondary Battery
Tomokazu Yamane, Akiyoshi Nakata, Toshiro Hirai, Zempachi Ogumi (Kyoto Univ.) EE2011-58 CPM2011-174		 The commercialization of zinc/air secondary battery is limited because of its low cycling life. Shape change and dendrit... [more] EE2011-58 CPM2011-174
pp.33-37
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2007-11-22
15:45		 Fukuoka Kitakyushu International Conference Center Memory Assignment Method Considering Orders of Operands for Massively Parallel Fine-grained SIMD Processor
Akira Kobashi, Ittetsu Taniguchi, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.), Kiyoshi Nakata (Renesas) VLD2007-104 DC2007-59		 In recent years, spread of data intensive multimedia applications equires high-performance in embedded systems.
Massiv... [more]		 VLD2007-104 DC2007-59
pp.91-96
VLD, IPSJ-SLDM 2007-05-10
13:30		 Kyoto Kyodai Kaikan Memory Assignment Method for Matrix Processing Array
Akira Kobashi, Ittetsu Taniguchi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.), Kiyoshi Nakata (Renesas) VLD2007-1		 MTA (MaTrix processing Array), which is developed by Renesas Technology Corp., can achieve high performance for digital ... [more] VLD2007-1
pp.1-6
ICD 2006-05-25
13:00		 Hyogo Kobe University A 40GOPS 250mW Massively Parallel Processor Based on Matrix Architecture -- A Very High Performance Processor IP for Mobile System-on-Chips --
Kiyoshi Nakata, Masami Nakajima, Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten (Renesas) 		We have developed a massively parallel processor based on Matrix architecture. This architecture achieved 40GOPS of 16-b... [more] ICD2006-25
pp.19-23
 Results 1 - 5 of 5  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan