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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2012-04-24
14:50		 Iwate Seion-so, Tsunagi Hot Spring (Iwate) Device-Conscious Circuit Designs for 0.5-V High-Speed Nanoscale CMOS LSIs
Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya (Hitachi), Masashi Horiguchi (Renesas) ICD2012-15		 The feasibility of 0.5-V memory-rich nanoscale CMOS LSIs was studied. First, nanoscale fully-depleted MOSFETs (FD MOS) a... [more] ICD2012-15
pp.79-84
SDM, ICD 2011-08-26
14:05		 Toyama Toyama kenminkaikan Sense Amplifier with Current Control Switch for Small-sized 0.5-V Gigabit-DRAM Arrays
Akira Kotabe, Yoshimitsu Yanagawa, Riichiro Takemura, Tomonori Sekiguchi, Kiyoo Itoh (Hitachi) SDM2011-90 ICD2011-58		  [more] SDM2011-90 ICD2011-58
pp.99-102
ICD 2009-04-13
13:30		 Miyagi Daikanso (Matsushima, Miyagi) [Invited Talk] Trend in Multi-Gigabit DRAM Technology and Low-Vt Small-Offset Gated Preamplifier for Sub-1-V Arrays
Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh (Hitachi, Ltd.,) ICD2009-2		  [more] ICD2009-2
pp.7-12
ICD, SDM 2005-08-19
13:50		 Hokkaido HAKODATE KOKUSAI HOTEL A 0.4-V High-Speed Long-Retention-Time DRAM Array with 12 F2 Twin Cell
Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa (Hitachi), Kazuhiko Kajigaya (ELPIDA), Takayuki Kawahara (Hitachi) 		We propose and evaluate a DRAM cell array with 12-F2 twin cell in terms of speed, retention time, and low-voltage operat... [more] SDM2005-152 ICD2005-91
pp.55-60
ICD 2004-12-16
10:00		 Hiroshima   Dynamic-Vth, Dual-Power-Supply SRAM Cell Using D2G-SOI for Low-Power SoC Application
Masanao Yamaoka, Kenichi Osada, Kiyoo Itoh, Ryuta Tsuchiya, Takayuki Kawahara (Hitachi, Ltd.) 		We developped two SRAM memory cells suitable for low-power SoC. The memory cells are composed of new FD-SOI transistors,... [more] ICD2004-183
pp.1-5
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