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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 8 of 8  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2012-03-07
14:10		 Oita B-con Plaza Power Efficient Design of Arithmetic Circuits Based on Embedded Memory Blocks in FPGA
Xinmu Yu (Waseda Univ.), Kiyoharu Hamaguchi (Osaka Univ.), Shinji Kimura (Waseda Univ.) VLD2011-140		  [more] VLD2011-140
pp.121-126
VLD, IPSJ-SLDM 2008-05-08
15:10		 Hyogo Kobe Univ. Checker Generation of Assertions with Local Variables for Model Checking
Sho Takeuchi, Kiyoharu Hamaguchi, Yosuke Kakiuchi, Toshinobu Kashiwabara (Osaka Univ.) 		To perform functional formal verification, model checking for
assertions has been used. It is difficult, however, to... [more]		 VLD2008-3
pp.13-18
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2007-11-20
11:20		 Fukuoka Kitakyushu International Conference Center An Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic
Hiroaki Shimizu, Kiyoharu Hamaguchi, Toshinobu Kashiwabara (Osaka Univ.) 		Model checking technique, which is a method to verify systems automatically, have attracted attentions. Model checking, ... [more] VLD2007-73 DC2007-28
pp.19-24
RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2006-11-28
09:25		 Fukuoka Kitakyushu International Conference Center Equivalence Checking using a Decidable Subclass of First-Order-Logic under Equivalence Constraints
Hiroaki Kozawa, Kiyoharu Hamaguchi, Toshinobu Kashiwabara (Osaka Univ.) 		 [more] VLD2006-52 DC2006-39
pp.5-10
RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2006-11-28
09:50		 Fukuoka Kitakyushu International Conference Center Bounded Model Checking for Assertions including Dynamic Local Variables
Sho Takeuchi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara (Osaka Univ.) 		 [more] VLD2006-53 DC2006-40
pp.11-16
RECONF, CPSY, VLD, IPSJ-SLDM 2006-01-17
16:55		 Kanagawa   Boolean Equivalence Checking Using a Subset of First-Order Logic
Atsushi Moritomo, Kiyoharu Hamaguchi, Toshinobu Kashiwabara (Osaka Univ.) 		(Advance abstract in Japanese is available) [more] VLD2005-96 CPSY2005-52 RECONF2005-85
pp.49-54
SIP, ICD, IE, IPSJ-SLDM 2005-10-21
15:30		 Miyagi Ichinobo, Sakunami-Spa A Monitor Generation Method for Formal Monitor-based Verification Considering Input Constraints
Yosuke Kakiuchi (Osaka Univ.), Akira Kitajima (Osaka Electro-Communication Univ.), Kiyoharu Hamaguchi, Toshinobu Kashiwabara (Osaka Univ.) 		In order to verify hardware module interfaces, various verification methods have been proposed. This paper focuses on fo... [more] SIP2005-127 ICD2005-146 IE2005-91
pp.73-78
CPSY, VLD, IPSJ-SLDM 2005-01-25
13:00		 Kanagawa   [Invited Talk] Basics and Goals of Assertion-Based Verification
Kiyoharu Hamaguchi (Osaka Univ.) 		 [more] VLD2004-102 CPSY2004-68
pp.29-34
 Results 1 - 8 of 8  /   
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