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Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] 2015-03-06
14:50
Kagoshima   A Resource Utilization Aware Method to Improve Throughput on RMT Processor
Taro Murata, Kensuke Kaneda, Masayoshi Takasu, Keigo Mizotani, Yusuke Hatori, Nobuyuki Yamasaki (Keio Univ.) CPSY2014-166 DC2014-92
SMT (Simultaneous MultiThreading) architecture is suitable for embedded processors which have area
constraints, it is b... [more]
CPSY2014-166 DC2014-92
pp.25-30
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-25
13:55
Kanagawa Hiyoshi Campus, Keio University An IPC Control Mechanism for Real-Time Processing on a Prioritized SMT Processor
Kensuke Kaneda, Kohei Matsumoto, Nobuyuki Yamasaki (Keio Univ) VLD2011-97 CPSY2011-60 RECONF2011-56
Although the SMT processor which performs two or more threads simultaneously can improve total throughput, the execution... [more] VLD2011-97 CPSY2011-60 RECONF2011-56
pp.37-42
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