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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2023-03-24 11:20 |
Kagoshima | Amagi Town Disaster Prevention Center (Tokunoshima) (Primary: On-site, Secondary: Online) |
Power Estimation Model for Directly-connected FPGA Clusters Kensuke Iizuka, Aika Kamei, Kazuei Hironaka, Hideharu Amano (Keio Univ.)  CPSY2022-45 DC2022-104 |
FPGA cluster is a promising platform not only in the cloud but in the 5G wireless base stations with limited power suppl... [more] | CPSY2022-45 DC2022-104 pp.66-71 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-29 11:10 |
Kumamoto | (Primary: On-site, Secondary: Online) |
A Message Passing Interface Library for High-Level Synthesis on M-KUBOS Multi-FPGA systems Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano (Keio Univ.) VLD2022-29 ICD2022-46 DC2022-45 RECONF2022-52 |
[more] | VLD2022-29 ICD2022-46 DC2022-45 RECONF2022-52 pp.61-66 |
| CPSY, DC, IPSJ-ARC [detail] | 2022-07-28 14:00 |
Yamaguchi | Kaikyo Messe Shimonoseki (Primary: On-site, Secondary: Online) |
Takumi Inage, Kensuke Iizuka, Hideharu Amano (Keio Univ.) CPSY2022-9 DC2022-9 |
(To be available after the conference date) [more] | CPSY2022-9 DC2022-9 pp.47-52 |
| RECONF | 2022-06-08 11:35 |
Ibaraki | CCS, Univ. of Tsukuba (Primary: On-site, Secondary: Online) |
Introduction of Power Monitoring Tool for FPGA Clusters and Power Analysis of FPGA Clusters Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano (Keio Univ) RECONF2022-18 |
Low power consumption is a significant advantage of FPGA clusters. This study reports the detailed power consumption an... [more] |
RECONF2022-18 pp.80-85 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-02 09:20 |
Online | Online | The Implementation of a Hybrid Router with Dynamic Communication Priority Changes on a Multi-FPGA System Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano (Keio Univ.) VLD2021-36 ICD2021-46 DC2021-42 RECONF2021-44 |
We are currently developing a multi-FPGA system, Flow-in-Cloud (FiC) system. FiC directly interconnects multiple middle-... [more] | VLD2021-36 ICD2021-46 DC2021-42 RECONF2021-44 pp.111-116 |
| RECONF | 2021-09-10 16:10 |
Online | Online | Multi-FPGA Based Hardware Acceleration for Genetic Data Analysis Imdad Ullah (Keio Univ.), Akram Ben Ahmed (AIST), Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano (Keio Univ.) RECONF2021-24 |
[more] | RECONF2021-24 pp.42-47 |
| CPSY, DC, IPSJ-ARC [detail] | 2021-07-20 15:15 |
Online | Online | CPSY2021-3 DC2021-3 |
[more] | CPSY2021-3 DC2021-3 pp.13-18 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2021-03-26 16:00 |
Online | Online | Implementation of Versatile Tensor Accelarator (VTA) on the Flow-in-Cloud FPGA system Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano (Keio Univ.) CPSY2020-69 DC2020-99 |
[more] | CPSY2020-69 DC2020-99 pp.115-120 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-26 10:30 |
Online | Online | VLD2020-58 CPSY2020-41 RECONF2020-77 |
(To be available after the conference date) [more] | VLD2020-58 CPSY2020-41 RECONF2020-77 pp.107-112 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2020-11-18 09:30 |
Online | Online | Comparing RISC-V RV32I and MIPS R3000 as a model processor for education Hideharu Amano, Kensuke Iizuka, Kohei Itoh (Keio Univ.) VLD2020-33 ICD2020-53 DC2020-53 RECONF2020-52 |
[more] | VLD2020-33 ICD2020-53 DC2020-53 RECONF2020-52 pp.122-126 |
| CPSY, DC, IPSJ-ARC [detail] | 2020-07-31 11:00 |
Online | Online | The next generation FiC with M-KUBOS board Hideharu Amano, Kazuei Hironaka, Kensuke Iizuka (Keio Univ.) CPSY2020-9 DC2020-9 |
[more] | CPSY2020-9 DC2020-9 pp.55-60 |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2020-01-22 14:20 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Implementation and Evaluation of a Router on a Multi-FPGA System Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Yugo Yamauchi, Kazuei Hironaka, Hideharu Amano (Keio Univ.) VLD2019-59 CPSY2019-57 RECONF2019-49 |
The trade-off between power efficiency and performance is important in large-scale computing systems like a datacenter. ... [more] | VLD2019-59 CPSY2019-57 RECONF2019-49 pp.31-36 |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2020-01-22 14:45 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Performance Evaluation of Using Multi-Switch on a Multi-FPGA System Kohei Ito, Kensuke Iizuka, Yugo Yamauchi, Kazuei Hironaka (Keio Univ.), Yao Hu, Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) VLD2019-60 CPSY2019-58 RECONF2019-50 |
Flow-in-Cloud(FiC) is a system which consists of multiple middle-range FPGAs connected by high-speed serial links, and i... [more] | VLD2019-60 CPSY2019-58 RECONF2019-50 pp.37-42 |
| CPSY, DC, IPSJ-ARC [detail] | 2019-07-25 09:45 |
Hokkaido | Kitami Civic Hall | Study and implementation of division of AlexNet into a multi-FPGA system Kensuke Iizuka, Hideharu Amano (Keio Univ.) CPSY2019-23 DC2019-23 |
(To be available after the conference date) [more] | CPSY2019-23 DC2019-23 pp.91-95 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2018-03-08 15:00 |
Shimane | Okinoshima Bunka-Kaikan Bldg. | Implementation GoogLeNet on multi FPGAs Kensuke Iizuka, Kazusa Musha, Hideharu Amano (Keio Univ) CPSY2017-141 DC2017-97 |
(To be available after the conference date) [more] | CPSY2017-141 DC2017-97 pp.191-196 |
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